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1 copyright ? cirrus logic, inc. 2007 (all rights reserved) cirrus logic, inc. http://www.cirrus.com CS5460A single phase, bi-direct ional power/energy ic features z energy data linearity: 0.1% of reading over 1000:1 dy namic range. z on-chip functions: (real) energy, i ? v, i rms and v rms , energy-to-pulse conversion z smart ?auto-boot? mo de from serial eeprom enables use without mcu. z ac or dc system calibration z mechanical counter/s tepper motor driver z meets accuracy spec for iec 687/1036, jis z typical power consumption <12 mw z interface optimized for shunt sensor z v vs. i phase compensation z ground-referenced signals with single supply z on-chip 2.5 v refere nce (max 60 ppm/c drift) z simple three-wire digi tal serial interface z watch dog timer z power supply monitor z power supply configurations va+ = +5 v; va- = 0 v; vd+ = +3.3 v to +5 v description the CS5460A is a highly integrated power mea- surement solution which combines two ? analog-to-digital converters (adcs), high-speed power calculation functions, and a serial interface on a single chip. it is designed to accurately mea- sure and calculate: real (true) energy, instantaneous power, i rms , and v rms for single phase 2- or 3-wire power metering applications. the CS5460A interfaces to a low-cost shunt resis- tor or transformer to measure current, and to a resistive divider or potential transformer to mea- sure voltage. the CS5460A features a bi-directional serial interface for communication with a microcontroller and a pulse output engine for which the average pulse frequency is proportional to the real power. the CS5460A has on-chip func- tionality to facilitate ac or dc system-level calibration. the ?auto-boot? feature allows the CS5460A to function ?stand-alone? and to initialize itself on sys- tem power-up. in auto-boot mode, the CS5460A reads the calibration data and start-up instructions from an external eeprom. in this mode, the CS5460A can operate without a microcontroller, in order to lower the total bill-of-materials cost. pga x10,x50 va+ vd+ iin+ iin- vin+ vin- vrefin vrefout va- xin xout cpuclk dgnd cs sdo sdi sclk int eout digital filter high pass filter voltage reference system clock /k clock generator serial interface power calculation engine (energy i*v i,v ) rms rms energy-to- pulse converter power monitor pfmon x1 x10 4 order ? modulator th reset digital filter calibration sram edir high pass filter 2 order modulator nd watch dog timer mode control / ? nov ?07 ds487f4
CS5460A 2 ds487f4 table of contents 1. characteristics and specifications ........................................................................ 5 analog characteristics ................................................................................................ 5 vrefout reference output voltage........................................................................ 7 5v digital characteristics............................................................................................ 7 3.3 v digital characteristics........................................................................................ 8 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 8 switching characteristics .......................................................................................... 9 2. overview .................................................................................................................. ........... 12 2.1 theory of operation ....................................................................................................... .. 12 2.1.1 ds modulators ................................................................................................... 12 2.1.2 high-rate digital low-pa ss filters ..................................................................... 12 2.1.3 digital compensation filters ............................................................................... 12 2.1.4 digital high-pass filters ...................................................................................... 12 2.1.5 overall filter re sponse ....................................................................................... 13 2.1.6 gain and dc offset adjustment .......................................................................... 13 2.1.7 real energy and rms computations ................................................................. 13 2.2 performing measurements ............................................................................................... 13 2.2.1 CS5460A linearity performance ......................................................................... 15 2.2.2 single computation cycle (c=0) ......... ................................................................ 15 2.2.3 continuous computation cycles (c=1) ............................................................... 16 2.3 basic application circuit configurations .......................................................................... 16 3. functional description ............................................................................................... 21 3.1 pulse-rate output ......................................................................................................... .. 21 3.2 pulse output for normal format, stepper motor format and mechanical counter format .............................................. 22 3.2.1 normal format .................................................................................................... 22 3.2.2 mechanical counter format ................................................................................ 23 3.2.3 stepper motor format ......................................................................................... 23 3.3 auto-boot mode using eeprom .............. ................ ................ ................ ............. ......... 24 3.3.1 auto-boot configuration ...................................................................................... 24 3.3.2 auto-boot data for eeprom ........ ................ ................ ................ ............. ......... 25 3.3.3 application note an225 ...................................................................................... 26 3.4 interrupt and watchdog timer ......................................................................................... 26 3.4.1 interrupt ............................................................................................................... 26 3.4.1.1 clearing the status register ............................................................... 26 3.4.1.2 typical use of the int pin ................................................................... 26 3.4.1.3 int active state .................................................................................. 26 3.4.1.4 exceptions ........................................................................................... 26 3.4.2 watch dog timer ................................................................................................ 26 3.5 oscillator characteristics ................................................................................................ .27 3.6 analog inputs ............................................................................................................. ...... 27 3.7 voltage reference ......................................................................................................... .. 27 3.8 calibration ............................................................................................................... ......... 27 3.8.1 overview of calibration process ...... ................................................................... 27 3.8.2 the calibration registers .................................................................................... 28 3.8.3 calibration sequence .......................................................................................... 28 3.8.4 calibration signal input level ............................................................................. 29 3.8.5 calibration signal frequency ........... ................................................................... 29 3.8.6 input configurations fo r calibrations ................................................................... 29 3.8.7 description of calibration algorithms .................................................................. 30 3.8.7.1 ac offset calibration sequence ......................................................... 30 3.8.7.2 dc offset calibration sequence ......................................................... 31
CS5460A ds487f4 3 3.8.7.3 ac gain calibrati on sequence ........................................................... 31 3.8.7.4 dc gain calibration sequence ......................................................... 31 3.8.8 duration of calibration sequence .... ................................................................... 31 3.9 phase compensation ...................................................................................................... 31 3.10 time-base calibration register ..................................................................................... 32 3.11 power offset register ............................. ...................................................................... 3 2 3.12 input protection - curren t limit ...................................................................................... 32 3.13 input filtering .......................................................................................................... ....... 34 3.14 protection against high-voltage and/or high-current surges ...................................... 37 3.15 improving rfi immunity ................................................................................................ 38 3.16 pcb layout ............................................................................................................... .... 38 4. serial port overview .................................................................................................... 38 4.1 commands (write only) .................................................................................................. 39 4.2 serial port interface ..................................................................................................... .... 42 4.3 serial read and write ..................................................................................................... 42 4.3.1 register write ..................................................................................................... 42 4.3.2 register read ..................................................................................................... 42 4.4 system initialization ..................................................................................................... .... 42 4.5 serial port initialization ................................................................................................ .... 43 4.6 CS5460A power states ................................................................................................... 43 5. register description ................................................................................................... 44 5.1 configuration register ..................................................................................................... .44 5.2 current channel dc offset register and vo ltage channel dc offset register .............. 46 5.3 current channel gain register and volta ge channel gain register............................... 46 5.4 cycle count register....................................................................................................... .46 5.5 pulse-rate register ........................................................................................................ .47 5.6 i,v,p,e signed output register results ........................................................................... 47 5.7 irms, vrms unsigned output register resu lts ............................................................. 47 5.8 timebase calibration register ......................................................................................... 47 5.9 power offset register ...................................................................................................... 48 5.10 current channel ac offset register and voltage channel ac offset register............. 48 5.11 status register and mask register .......... ...................................................................... 48 5.12 control register.......................................................................................................... .... 50 6. pin description ........................................................................................................... ...... 51 7. package dimensions ...................................................................................................... 53 8. ordering information .................................................................................................. 54 9. change history ............................................................................................................ .... 54
CS5460A 4 ds487f4 list of figures figure 1. CS5460A read and write timing diag rams.................................................................. 10 figure 2. CS5460A auto-boot sequence timing.... ...................................................................... 11 figure 3. data flow. ........................................................................................................... ........... 13 figure 4. voltage input filter characteristics ................................................................................ 1 4 figure 5. current input filter characteristics ................................................................................ 1 4 figure 6. typical connection diagram (one-phase 2-wire, direct connect to power line) ........ 17 figure 7. typical connection diagram (one-pha se 2-wire, isolated from power line) ............... 18 figure 8. typical connection diagram (one-phase 3-wire)......................................................... 19 figure 9. typical connection diagram (one-phase 3-wire - no neutral av ailable)..................... 20 figure 10. time-plot representation of pulse outpu t for a typical burst of pulses (normal format)23 figure 11. mechanical counter fo rmat on eout and edir ........................................................ 23 figure 12. stepper moto r format on eout and edir ................................................................. 24 figure 13. typical interface of eeprom to CS5460A.. ................ ............. ............. ............. ......... 24 figure 14. timing diagram for auto-boot sequenc e .................................................................... 25 figure 15. oscillator connection ............................................................................................... .... 27 figure 16. system calibration of gain. ......................................................................................... 30 figure 17. system calibration of offset. ....................................................................................... 30 figure 18. calibration data fl ow............................................................................................... .... 30 figure 19. example of ac gain calibration ........ .......................................................................... 31 figure 20. input protection for single-ended input configurations ............................................... 37 figure 21. CS5460A register dia gram......................................................................................... 44 list of tables table 1. differential input voltage vs. output co de ...................................................................... 14 table 2. available range of 0.1% output linearity, with default settings in the gain/offset regist ers. ........................................................... 15 table 3. default register values upon reset even t ..................................................................... 43
CS5460A ds487f4 5 1. characteristic s & specifications analog characteristics (t a = -40 c to +85 c; va+ = vd+ = +5 v 10%; vref in = +2.5 v; va- = agnd = 0 v; mclk = 4.096 mhz, k = 1; n = 4000 ==> owr = 4000 sps.)(see notes 1, 2, 3, 4, and 5.) notes: 1. bipolar offset errors and full-scale ga in errors for the current and voltage channels refer to the respective irms register and vrms register output, when the device is ope rating in ?continuous computat ion cycles? data acquisition mode, after offset/gain system calibr ation sequences have been ex ecuted. these specs do not apply to the error of the instantaneous current/voltage register output. 2. specifications guaranteed by design, characterization, and/or test. 3. analog signals are relative to va- and di gital signals to dgnd unless otherwise noted. 4. in requiring va+ = vd+ =5 v 10%, note that it is allowable for va+, vd+ to differ by as much as 200 mv, as long as va+ > vd+. 5. note that ?sps? is an abbreviation for units of ?samples per second?. 6. effective input impedance (zin) is determined by clock frequency ( dclk) and input capacitance (ic). zin = 1/(ic*dclk/4). note that dclk = mclk / k. parameter symbol min typ max unit accuracy (both channels) common mode rejection (dc, 50, 60 hz) cmrr 80 - - db offset drift (without the high pass filter) - 5 - nv/c analog inputs (current channel) maximum differential input voltage range (gain = 10) {(v iin+ ) - (v iin- )} (gain = 50) i in - - - - 500 100 mv p-p mv p-p total harmonic distortion thd i 80 - - db common mode + signal on iin+ or iin- (gain = 10 or 50) -0.25 - va+ v crosstalk with voltage channel at full scale (50, 60 hz) - - -115 db input capacitance (gain = 10) (gain = 50) c in - - 25 25 - - pf pf effective input impedance (note 6) (gain = 10) (gain = 50) z ini z ini - - 30 30 - - k ? k ? noise (referred to input) (gain = 10) (gain = 50) - - - - 20 4 v rms v rms accuracy (current channel) bipolar offset er ror (note 1) vos i - 0.001 - %f.s. full-scale error (note 1) fse i - 0.001 - %f.s. analog inputs (voltage channel) maximum differential input voltage range {(v vin+ ) - (v vin- )} v in --500mv p-p total harmonic distortion thd v 62 - - db common mode + signal on vin+ or vin- va- - va+ v crosstalk with current channel at full scale (50, 60 hz) - - -70 db input capacitance c inv -0.2-pf effective input impedance (note 6) z inv -5-m ? noise (referred to input) - - 250 v rms accuracy (voltage channel) bipolar offset er ror (note 1) vos v - 0.01 - %f.s. full-scale error (note 1) fse v - 0.01 - %f.s.
CS5460A 6 ds487f4 analog characteristics (continued) notes: 7. the minimum fscr is limited by the maximum allowed gain register value. 8. all outputs unloaded. all inputs cmos level. 9. definition for psrr: vrefin tied to vrefou t, va+ = vd+ = 5 v, a 150 mv zero-to-peak sinewave (frequency = 60 hz) is imposed onto the +5 v supply voltage at va+ and vd+ pins. the ?+? and ?-? input pins of both input channels are shorted to va-. then the CS5460A is commanded to ?continuous computation cycles? data acquisition mode, and digital output data is collected for the channel under test. the zero-peak value of the digital sinusoidal output signal is determined, and this value is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel?s inputs, in order to cause the same digital sinusoidal output. this voltage is then defined as veq. psrr is then (in db): 10. when voltage level on pfmon is sagging, and lsd bit is 0, the voltage at which lsd bit is set to 1. 11. assuming that the lsd bit has been set to 1 (because pfmon voltage fell below pmlo), then if/when the pfmon voltage starts to rise again, pmhi is th e voltage level (on pfmon pin) at which the lsd bit can be permanently reset back to 0 (without instantaneo usly changing back to 1). attempts to reset the lsd bit before this condit ion is true will not be successful. this condition indicates that power has been restored. typically, for a given sample, the pm hi voltage will be ~100 mv above the pmlo voltage. parameter symbol min typ max unit dynamic characteristics phase compensation range (voltage channel, 60 hz) -2.4 - +2.5 high rate filter output word rate (both channels) owr - dclk/1024 - sps input sample rate dclk = mclk/k - dclk/8 - sps full scale dc calibration range (note 7) fscr 25 - 100 %f.s. channel-to-channel time-shift error (when pc[6:0] bits are set to ?0000000?) 1.0 s high pass filter pole frequency -3 db - 0.5 - hz power supplies power supply currents (active state) i a+ i d+ (vd+ = 5 v) i d+ (vd+ = 3.3 v) psca pscd pscd - - - 1.3 2.9 1.7 - - - ma ma ma power consumption active state (vd+ = 5 v) (note 8) active state (vd+ = 3.3 v) stand-by state sleep state pc - - - - 21 11.6 6.75 10 25 - - - mw mw mw w power supply rejection ratio (50, 60 hz) for current channel (gain = 10) (note 9) (gain = 50) psrr psrr 56 75 - - - - db db power supply rejection ratio (50, 60 hz) for voltage channel (note 9) psrr - 65 - db pfmon power-fail detect thre shold (note 10) pmlo 2.3 2.45 - v pfmon ?power-restored? detect threshold (note 11) pmhi - 2.55 2.7 v psrr 20 0.150v v eq ------------------ - ?? ?? ?? log ? =
CS5460A ds487f4 7 vrefout referenc e output voltage notes: 12. the voltage at vrefout is measured across th e temperature range. from these measurements the following formula is used to calculate the vrefout temperature coefficient:. 5v digital characteristics (t a = -40 c to +85 c; va+ = vd+ = 5 v 10% va-, dgnd = 0 v) (see notes 3, 4, and 13) 13. note that the 5 v characteristics are guaranteed by characterization. only the more rigorous 3.3 v digital characteristics are actually verified during production test. 14. applies to all input pins except xin pin (leakag e current < 50 a) and mode pin (leakage current < 25 a). parameter symbol min typ max unit reference output output voltage refout +2.4 - +2.6 v vrefout temperature coefficient (note 12) t vrefout -3060ppm/c load regulation (output current 1 a source or sink) ? v r -610mv reference input input voltage range vrefin +2.4 +2.5 +2.6 v input capacitance - 4 - pf input cvf current - 25 - na parameter symbol min typ max unit high-level input voltage all pins except xin, sclk and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage all pins except xin, sclk, and reset xin sclk and reset v il - - - - - - 0.8 1.5 0.2 vd+ v v v high-level output voltage (except xout) i out =+5ma v oh (vd+) - 1.0 - - v low-level output voltage (except xout) i out =-5ma v ol --0.4v input leakage current (note 14) i in -110a high impedance state leakage current i oz --10a digital output pin capacitance c out -5-pf (vrefout max - vrefout min ) vrefout avg t a max - t a min 1 (() ) 1.0 x 10 () 6 t vrefout =
CS5460A 8 ds487f4 3.3 v digital characteristics (t a =-40c to +85c; va+=5v10%, vd+=3.3v10% ; va-, dgnd = 0 v) (see notes 3, 4, and 13) notes: 15. all measurements performed under static conditions. 16. if vd+ = 3 v and if xin input is generated using cr ystal, then xin frequenc y must remain between 2.5 mhz - 5.0 mhz. if using o scillator, full xin frequency range is available, see switching characteristics . absolute maximum ratings (dgnd = 0 v; see note 17) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 17. all voltages with respect to ground. 18. va+ and va- must satisfy {(va+) - (va-)} +6.0 v. 19. vd+ and va- must sati sfy {(vd+) - (va-)} +6.0 v. 20. applies to all pins including continuous over-vol tage conditions at the analog input (ain) pins. 21. transient current of up to 10 0 ma will not cause scr latch-up. 22. maximum dc input current for a power supply pin is 50 ma. 23. total power dissipation, including all input currents and output currents. parameter symbol min typ max unit high-level input voltage all pins except xin, xout, sclk, and reset xin sclk and reset v ih 0.6 vd+ (vd+) - 0.5 0.8 vd+ - - - - - - v v v low-level input voltage all pins except xin, xout, sclk, and reset xin sclk and reset v il - - - - - - 0.48 0.3 0.2 vd+ v v v high-level output voltage (except xin, xout) i out =+5ma v oh (vd+) - 1.0 - - v low-level output voltage (except xin, xout) i out =-5ma v ol --0.4v input leakage current (note 14) i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf parameter symbol min typ max unit dc power supplies (notes 18 and 19) positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 +0.3 - - - +6.0 +6.0 -6.0 v v v input current, any pin except supplies(note 20, 21, and 22) i in --10ma output current i out --25ma power dissipation (note 23) p d --500mw analog input voltage all analog pins v ina (va-) - 0.3 - (va+) + 0.3 v digital input voltage all digital pins v ind dgnd - 0.3 - (vd+) + 0.3 v ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c
CS5460A ds487f4 9 switching characteristics (t a = -40 c to +85 c; va+ = 5.0 v 10%; vd+ = 3.0 v 10% or 5.0 v 10%; va- = 0.0 v; logic levels: logic 0 = 0.0 v, logic 1 = vd+; cl = 50 pf)) notes: 24. device parameters are specified with a 4.096 mhz clock, yet, clocks between 3 mhz to 20 mhz can be used. however, for input frequencies over 5 mhz, an external oscillator must be used. 25. if external mclk is used, then duty cycle must be between 45% and 55% to maintain this specification. 26. specified using 10% and 90% points on wave-form of interest. output loaded with 50 pf. 27. oscillator start-up time varies with crystal parameters. this specificat ion does not apply when using an external clock source. parameter symbol min typ max unit master clock frequencycryst al/internal gate oscillator (note 24) mclk 2.5 4.096 20 mhz master clock duty cycle 40 - 60 % cpuclk duty cycle (note 25) 40 60 % rise times any digital input except sclk (note 26) sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times any digital input except sclk (note 26) sclk any digital output t fall - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 4.096 mhz (note 27) t ost -60-ms serial port timing serial clock frequency sclk - - 2 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns sdi timing cs falling to sclk rising t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo timing cs falling to sdi driving t 7 -2050ns sclk falling to new data bit t 8 -2050ns cs rising to sdo hi-z t 9 -2050ns auto-boot timing serial clock pulse width high pulse width low t 10 t 11 8 8 mclk mclk mode setup time to reset rising t 12 50 ns reset rising to cs falling t 13 48 mclk cs falling to sclk rising t 14 100 8 mclk sclk falling to cs rising t 15 16 mclk cs rising to driving mode low (to end auto-boot sequence). t 16 50 ns sdo guaranteed setup time to sclk rising t 17 100 ns
CS5460A 10 ds487f4 cs sclk msb msb - 1 lsb t 2 t 1 t 3 sdi msb msb - 1 lsb command time 8 sclks lsb t 6 msb msb - 1 lsb msb msb - 1 high byte mid byte low byte t t 45 sdi write timing (not to scale) cs sdo sclk msb msb - 1 lsb t 2 t 1 t 8 t 7 sdi msb msb - 1 lsb command time 8 sclks lsb t 9 msb msb - 1 lsb msb msb - 1 high byte mid byte low byte m u s t s t r o b e " s y n c 0 " c o m m a n d o n s d i w h e n r e a d i n g e a c h b y t e o f d a t a f r o m s d o . sdo read timing (not to scale) figure 1. CS5460A read and write timing diagrams
CS5460A ds487f4 11 res sdi sclk t 8 t 14 t 13 t 1 1 t 10 sdo cs t 5 t 4 data from eeprom (output) (output) (output) (input) mode (input) t 12 t 15 t 16 stop bit last 8 bits (input) t 17 figure 2. CS5460A auto-boot sequence timing
CS5460A 12 ds487f4 2. overview the CS5460A is a cmos monolithic power mea- surement device with a real power/energy compu- tation engine. the CS5460A combines two programmable gain amplifiers, two ? modulators, two high rate filters, system calibration, and rms/power calculation functions to provide instan- taneous voltage/current/power data samples as well as periodic computation results for real (bill- able) energy, v rms , and i rms . in order to accom- modate lower cost metering applications, the CS5460A can also generate pulse-train signals on certain output pins, for which the number of pulses emitted on the pins is proportional to the quantity of real (billable) energy registered by the device. the CS5460A is optimized for power measure- ment applications and is designed to interface to a shunt or current transformer to measure current, and to a resistive divider or potential transformer to measure voltage. to accommodate various input voltage levels, the current channel includes a pro- grammable gain amplifier (pga) which provides two full-scale input levels, while the voltage chan- nel?s pga provides a single input voltage range. with a single +5 v supply on va+/-, both of the CS5460A?s input channels can accomodate com- mon mode + signal levels between -0.25 v and va+. the CS5460A includes two high-rate digital filters (one per channel), which decimate/integrate the output from the 2 ? modulators. the filters yield 24-bit output data at a (mclk/k)/1024 output word rate (owr). the owr can be thought of as the ef- fective sample frequency of the voltage channel and the current channel. to facilitate communication to a microcontroller, the CS5460A includes a simple three-wire serial interface which is spi? and microwire? compati- ble. the serial port has a schmitt trigger input on its sclk (serial clock) and reset pins to allow for slow rise time signals. 2.1 theory of operation a computational flow diagram for the two data paths is shown in fig. 3. the reader should refer to this diagram while reading the following data pro- cessing description, which is covered block-by-block. 2.1.1 ? modulators the analog waveforms at the voltage/current chan- nel inputs are subject to the gains of the input pgas (not shown in figure 3). these waveforms are then sampled by the delta-sigma modulators at a rate of (mclk/k)/8 sps. 2.1.2 high-rate di gital low-pass filters the data is then low-pass filtered, to remove high-frequency noise from the modulator output. referring to figure 3, the high rate filter on the volt- age channel is implemented as a fixed sinc 2 filter. the current channel uses a sinc 4 filter, which al- lows the current channel to make accurate mea- surements over a wider span of the total input range, in comparison to the accuracy range of the voltage channel. (this subject is discussed more in section 2.2.1 ) also note from figure 3 that the digital data on the voltage channel is subjected to a variable time-de- lay filter. the amount of delay depends on the val- ue of the seven phase compensation bits (see phase compensation ). note that when the phase compensation bits pc[6:0] are set to their default setting of ?0000000? (and if mclk/k = 4.096 mhz) then the nominal time delay that is imposed on the original analog voltage input signal, with respect to the original analog current input signal, is ~1.0 s. this translates into a delay of ~0.0216 degrees at 60 hz. 2.1.3 digital compensation filters the data from both channels is then passed through two fir compensation filters, whose pur- pose is to compensate for the magnitude roll-off of the low-pass filtering operation (mentioned earli- er). 2.1.4 digital high-pass filters both channels provide an optional high-pass filter (denoted as ?hpf? in figure 3) which can be en- gaged into the signal path, to remove the dc con- tent from the current/voltage signal before the rms/energy calculations are made. these filters are activated by enabling certain bits in the config- uration register. if the high-pass filter is engaged in only one of the two channels, then the all-pass filter (see ?apf? in
CS5460A ds487f4 13 figure 3) will be enabled on the other channel; in order to preserve the relative phase relationship between the voltage-sense and current-sense in- put signals. for example, if the hpf is engaged for the voltage channel, but not the current channel, then the apf will be engaged in the current channel, to nullify the additional phase delay introduced by the high-pass filter in the current channel. 2.1.5 overall filter response when the CS5460A is driven with a 4.096 mhz clock (k = 1), the composite magnitude response (over frequency) of the voltage channel?s input fil- ter network is shown in figure 4, while the com- posite magnitude response of the current channel?s input filter netwo rk is given in figure 5. note that the composite filter response of both channels scales with mclk frequency and k. 2.1.6 gain and dc offset adjustment after filtering, the instantaneous voltage and cur- rent digital codes are s ubjected to offset/gain ad- justments, based on the values in the dc offset registers (additive) and the gain registers (multipli- cative). these registers are used for calibration of the device (see section 3.8, calibration ). after off- set and gain, the 24-bit instantaneous data sample values are stored in the instantaneous voltage and current registers. 2.1.7 real energy and rms computations the digital instantaneous voltage and current data is then processed further. referring to figure 3, the instantaneous voltage/current data samples are multiplied together (one multiplication for each pair of voltage/current samples) to form instantaneous (real) power samples. after each a/d conversion cycle, the new instantaneous power sample is stored in the instantaneous power register. the instantaneous power samples are then grouped into sets of n samples (where n = value in cycle count register). the cumulative sum of each successive set of n instantaneous power is used to compute the result stored in the energy register, which will be proportional to the amount of real energy registered by the device during the most recent n a/d conversion cycles. note from figure 3 that the bits in this running energy sum are right-shifted 12 times (divided by 4096) to avoid overflow in the energy register. rms calcu- lations are also performed on the data using the last n instantaneous voltage/current samples, and these results can be read from the rms voltage register and the rms current register. 2.2 performing measurements to summarize section 2.1, the CS5460A performs measurements of instantaneous current and in- stantaneous voltage, and from this, performs com- putations of the corresponding instantaneous power, as well as periodic calculations of real en- ergy, rms current, and rms voltage. these mea- surement/calculation results are available in the form of 24-bit signed and unsigned words. the scaling of all output words is normalized to unity voltage ? sinc 2 + x v* gn x v * current sinc 4 + x i* gn x x tbc * delay reg delay reg fir hpf apf configuration register * pc[6:0] bits x i* rms n v* rms n 4096 etof e* e e out dir pulse-rate* * denotes register name ? hpf apf fir sinc 2 i * p * n sinc 2 - - i acoff * i dcoff * v acoff * v dcoff * + p off * n n figure 3. data flow.
CS5460A 14 ds487f4 full-scale. note that the 24-bit signed output words are expressed in two?s complement format. the 24-bit data words in the CS5460A output registers represent values between 0 and 1 (for unsigned output registers) or between -1 and +1 (for signed output registers). a register value of 1 represents the maximum possible value. note that a value of 1.0 is never actually obtained in the registers of the CS5460A. as an illustration, in any of the signed output registers, the maximum register value is [(2^23 - 1) / (2^23)] = 0.999999880791. after each a/d conversion, the crdy bit will be asserted in the status register, and the int pin will also be- come active if the crdy bit is unmasked (in the mask register). the assertion of the crdy bit in- dicates that new instantaneous 24-bit voltage and current samples have been collected, and these two samples have also been multiplied together to provide a corresponding instantaneous 24-bit pow- er sample. table 1 conveys the typical relationship between the differential input voltage (across the ?+? and ?-? input pins of the voltage channel input) and the cor- responding output code in the instantaneous volt- age register. note that this table is applicable for the current channel if the current channel?s pga gain is set for the ?10x? gain mode. the v rms , i rms , and energy calculations are up- dated every n conversions (which is known as 1 ? computation cycle ?), where n is the value in the cycle count register. at the end of each computa- tion cycle, the drdy bit in the mask register will be set, and the int pin will become active if the drdy bit is unmasked. drdy is set only after each computation cycle has completed, whereas the crdy bit is asserted after each individual a/d conver sion. bits asserted by the CS5460A must be cleared before being assert- ed again. if the cycle coun t register value (n) is set to 1, all output calculations are instantaneous, and drdy will indicate when instantaneous calcu- lations are finished, just like the crdy bit. for the rms results to be valid, the cycle-count register must be set to a value greater than 10. the computation cycle frequency is derived from the master clock, and has a value of (mclk/k)/(1024*n). under default conditions, with -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 frequency (hertz) gain (db) 0 200 400 600 800 1000 1200 1400 1600 1800 2000 figure 4. voltage input filter characteristics input voltage (dc) output code (hexidecimal) output code (decimal) +250 mv 7fffff 8388607 14.9 nv to 44.7 nv 000001 1 -14.9 nv to 14.9 nv 000000 0 -44.7 nv to -14.9 nv ffffff -1 -250 mv 800000 -8388608 table 1. differential input voltage vs. output code -2.5 -2 -1.5 -1 -0.5 0 0.5 0 200 400 600 800 1000 1200 1400 1600 1800 2000 gain (db) frequency (hertz) figure 5. current input filter characteristics
CS5460A ds487f4 15 a 4.096 mhz clock at xin, and k = 1, instanta- neous a/d conversions for voltage, current, and power are performed at a 4000 sps rate, whereas i rms , v rms , and energy calculations are per- formed at a 1 sps rate. 2.2.1 CS5460A linearity performance table 2 lists the range of input levels (as a percent- age of full-scale) over wh ich the (linearity + varia- tion) of the results in the vrms, irms and energy registers are guaranteed to be within 0.1 % of reading after the completion of each successive computation cycle. note that until the CS5460A is calibrated (see calibration) the accuracy of the CS5460A with respect to a reference line-voltage and line-current level on the power mains is not guaranteed to within 0.1%. after both channels of the device are calibrated for offset/gain, the 0.1% of reading spec will also reflect accuracy of the vrms, irms, and energy register results. finally, observe that the maximum (full-scale) differential input voltage for the voltage channel (and current channel, when its pga is set for 10x gain) is 250 mv (nominal). if the gain registers of both channels are set to 1 (default) and the two dc offset registers are set to zero (default), then a 250mv dc signal applied to the voltage/current inputs will measure at (or near) the maximum value of 0.9999... in the rms current/voltage registers. remember that the rms value of a 250 mv (dc) signal is also 250 mv. however, for either input channel, it would not be practical to in- ject a sinusoidal voltage with rms value of 250 mv. this is because when the instantaneous value of such a sine wave is at or near the level of its positive/negative peak regions (over each cy- cle), the voltage level of this signal would exceed the maximum differential input voltage range of the input channels. the largest sine wave voltage sig- nal that can be presented across the inputs, with no saturation of the inputs, is: 250 mv / sqrt(2) = ~176.78 mv (rms), which is ~70.7% of full-scale. this would imply that for the current channel, the (linearity+variation) tol- erance of the rms measurements for a purely si- nusoidal 60 hz input signal could be measured to within 0.1% of reading over a magnitude range of 0.2% - 70.7% of the maximum full-scale differen- tial input voltage level. the range over which the (linearity + variation) will remain within 0.1% can often be increased by se- lecting a value for the cycle-count register such that the time duration of one computation cycle is equal to (or very close to) a whole-number of pow- er-line cycles (and n must be greater than or equal to 4000). for example, with the cycle count set to 4200, the 0.1% of reading (linearity + variation) range for measurement of a 60 hz sinusoidal cur- rent-sense voltage signal can be increased beyond the range of 0.2% - 70.7%. the accuracy range will be increased because (4200 samples / 60 hz) is a whole number of cycles (70). note that this in- crease in the measurement range refers to an ex- tension of the low end of the input scale (i.e., this does not extend the high-end of the range above 100% of full-scale). this enables accurate mea- surement of even smaller power-line current lev- els, thereby extending t he load range over which the power meter can make accurate energy mea- surements. increasing the accuracy range can be beneficial for power metering applications which require accurate power metering over a very large load range. 2.2.2 single computation cycle (c=0) note that ?c? refers to the value of the c bit, con- tained in the ?start conversions? command (see section 4.1). this commands instructs the CS5460A to perform conversions in ?single compu- tation cycle? data acquisi tion mode. based on the value in the cycle count register, a single compu- tation cycle is performed after a ?start conversions? command is sent to the serial interface. after the computations are complete, drdy is set. 32 sclks are then needed to read out a calculation energy vrms irms range (% of fs) 0.1% - 100% 50% - 100% 0.2% - 100% max. differential input not applicable v-channel: 250 mv i-channel: 250 mv 10x 50 mv 50x linearity 0.1% of reading 0.1% of reading 0.1% of reading table 2. available range of 0.1% output linearity, with default settings in the gain/offset registers.
CS5460A 16 ds487f4 result from one of several result registers. the first 8 sclks are used to clock in the command to de- termine which register is to be read. the last 24 sclks are used to read the desired register. after reading the data, the serial port remains in the ac- tive state , and waits for a new command to be is- sued. (see section 3 for more details on reading register data from the CS5460A). 2.2.3 continuous computation cycles (c=1) when c = 1, the CS5460A will perform conversions in ?continuous computati on cycles? data acquisition mode. based on the information provided in the cy- cle count register, computation cycles are repeat- edly performed on the voltage and current channels (after every n conversi ons). computation cycles cannot be started/stopped on a ?per-channel? basis. after each computation cycle is completed, drdy is set. thirty-two sclks are then needed to read a register. the first 8 sclks are used to clock in the command to determine which results register is to be read. the last 24 sclks are used to read out the 24-bit calculation result. while in this acquisition mode, the designer/programmer may choose to ac- quire (read) only those calc ulations required for their particular application, as drdy repeatedly in- dicates the availability of new data. note again that the mcu firmware must reset the drdy bit to ?0? before it can be asserted again. referring again to figure 3, note that within the irms and vrms data paths, prior to the square-root operation, the instantaneous voltage/current data is low-pass filtered by a sinc 2 filter. then the data is decimated to every nth sample. because of the sinc 2 filter operation, the first output for each chan- nel will be invalid (i.e. al l rms calculations are in- valid in the ?single co mputation cycle? data acquisition mode and the first rms calculation re- sults will be invalid in the ?continuous computation cycles? data acquisition mode). however, all ener- gy calculations will be va lid since energy calcula- tions do not require this sinc 2 operation. if the ?start conversions? command is issued to the CS5460A (see section 4.1, commands (write only) ), and if the ?c? bit in this command is set to a value of ?1?, the device will remain in its active state . once commanded into continuous computation cycles data acquisition mode, the CS5460A will continue to perform a/d conversions on the volt- age/current channels, as well as all subsequent calculations, until: 1) the ?power-up/halt? command is received through the serial interface, or 2) loss of power, or 3) the rs bit in the configuration register is as- serted (?software reset?), or 4) the /reset pin is asserted and then de-assert- ed (?hardware reset?). 2.3 basic application circuit configurations figure 6 shows the CS5460A connected to a ser- vice to measure power in a single-phase 2-wire system operating from a single power supply. note that in this diagram the shunt resistor used to mon- itor the line current is connected on the ?line? (hot) side of the power mains. in most residential power metering applications, the power meter?s cur- rent-sense shunt resistor is intentionally placed on the ?hot? side of the power mains in order to help detect any attempt by the subscriber to steal pow- er. in this type of shunt-resistor configuration, note that the common-mode level of the CS5460A must be referenced to the hot side of the power line. this means that the common-mode potential of the CS5460A will typically osci llate to very high posi- tive voltage levels, as well as very high negative voltage levels, with respect to earth ground poten- tial. the designer must therefore be careful when attempting to interface the CS5460A?s digital out- put lines to an external digital interface (such as a lan connection or other communication network). such digital communication networks may require that the cmos-level digital interface to the meter is referenced to an earth-ground. in such cases, the CS5460A?s digital serial interface pins must be iso- lated from the external digital interface, so that there is no conflict between the ground references of the meter and the external interface. the CS5460A and associate circuitry should be en- closed in a protective insulated case when used in this configuration, to av oid risk of harmful electric shock to humans/animals/etc. figure 7 shows how the same single-phase two-wire system can be metered while achieving
CS5460A ds487f4 17 complete isolation from the power lines. this isola- tion is achieved using three transformers. one transformer is a general-purpose voltage trans- former, used to supply the on-board dc power to the CS5460A. a second transformer is a high-pre- cision, low-impedance voltage transformer (often called a ?potential transformer?) with very little roll-off/phase delay, even at the higher harmonics. a current transformer is then used to sense the line current. a burden resistor placed across the sec- ondary of the current transformer creates the cur- rent-sense voltage signal, for the CS5460A?s current channel inputs. because the CS5460A is not directly connected to the power mains, isola- tion is not required for the CS5460A?s digital inter- face. figure 8 shows the CS5460A configured to mea- sure power in a single-phase 3-wire system. in many 3-wire residential power systems within the united states, only the two line terminals are available (neutral is not available). figure 9 shows how the CS5460A can be configured to meter a 3-wire system when no neutral is available. va+ vd+ 0.1 f 100 f 500 ? 470 nf 500 n r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source serial data interface reset 17 2 1 24 19 cs 7 sdi 23 sdo 6 sclk 5 int 20 edir eout 0.1 f vrefin 12 vrefout 11 va- dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f c 10 k ? 5k ? l r shunt v+ * * refer to input protection CS5460A * ** refer to input filtering r v- * r i- * r i+ * c i+ * * isolation 120 vac mech. counter stepper motor or 22 21 ? + note: current channel input measures voltage (just like voltage input). c v- ** c i- ** c ** vdiff c ** idiff figure 6. typical connection diagram (one-phase 2-wire, direct connect to power line)
CS5460A 18 ds487f4 va+ vd+ 0.1 f 200 f 200 n 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int edir 22 eout 21 0.1 f vrefin 12 vrefout 11 va- dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f 10 k ? 5k ? l * refer to input protection m:1 r n:1 low phase-shift potential transformer current transformer CS5460A ** refer to input filtering r v+ * r v- * c vdiff ** r i- * r i+ * c ** burden idiff voltage transformer 120 vac 12 vac 12 vac ? 200 ? serial data interface 19 7 23 6 5 20 mech. counter stepper motor or 1k ? 1k ? 1k ? 1k ? + note: current channel input measures voltage (just like voltage input). c v+ ** c v- ** c i+ ** c i- ** figure 7. typical connection diagram (one-phase 2-wire, isolated from power line)
CS5460A ds487f4 19 va+ vd+ 0.1 f 100 f 500 ? 470 nf 500 ? n r 3 r 4 r burden 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sd sdo sclk int edir eout 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f l 1 l 2 10 k ? 5k ? va- * refer to input protection r 1 r 2 to service ** refer to input filtering r i+ * r i- * 22 21 mech. counter stepper motor or 1k ? 1k ? 120 vac 120 vac 240 vac serial data interface 19 7 23 6 5 20 i earth ground c ** idiff c ** vdiff + note: current channel input measures voltage (just like voltage input). c i+ ** c ** i- c v+ ** c ** v- CS5460A figure 8. typical connection diagram (one-phase 3-wire)
CS5460A 20 ds487f4 va+ vd+ CS5460A 0.1 f 1 k ? 235 nf 500 ? r 1 r 2 10 ? 14 vin+ 9 vin- iin- 10 16 15 iin+ pfmon cpuclk xout xin optional clock source reset 17 2 1 24 cs sdi sdo sclk int edir eout 0.1 f vrefin 12 vrefout 11 dgnd 13 4 3 to service 2.5 mhz to 20 mhz 0.1 f l 1 l 2 10 k ? 5k ? va- c v+ * refer to input protection * to service * ** refer to input filtering r i+ * r i- * r v- * serial data interface 19 7 23 6 5 20 isolation 22 21 mech. counter stepper motor or r burden 1k ? 1k ? 240 vac + note: current channel input measures voltage (just like voltage input). c ** v- c ** vdiff c i+ ** c ** i- c ** idiff 100 f figure 9. typical connection diagram (one-phase 3-wire - no neutral available)
CS5460A ds487f4 21 3. functional description 3.1 pulse-rate output as an alternative to reading the real energy through the serial port, the eout and edir pins provide a simple interface with which signed ener- gy can be accumulated. each eout pulse repre- sents a predetermined quantity of energy. the quantity of energy represented in one pulse can be varied by adjusting the value in the pulse-rate register. corresponding pulses on the edir out- put pin signify that the sign of the energy is nega- tive. note that these pulses are not influenced by the value of the cycle-count register, and they have no reliance on the computation cycle, de- scribed earlier. with mclk = 4.096 mhz, k = 1, the pulses will have an average frequency (in hz) equal to the frequency setting in the pulse rate register when the input signals into the voltage and current channels cause full-scale readings in the instantaneous voltage and current registers. when mclk/k is not equal to 4.096 mhz, the pulse-rate should be scaled by a factor of 4.096 mhz / (mclk/k) to get the actual output pulse-rate. example #1: for a power line with maximum rat- ed levels of 250 v (rms) and 20 a (rms), the pulse-frequency on the eout pin needs to be ?ir? = 100 pulses-per-second (100 hz) when the rms-voltage and rms-current levels on the power line are 220 v and 15 a respectively. to meet this requirement, the pulse-rate frequency (?pr?) in the pulse-rate register must be set accordingly. after calibration, the first step to finding the value of ?pr? is to set the voltage and current sensor gain constants, k v and k i , such that there will be ac- ceptable voltage levels on the CS5460A inputs when the power line voltage and current levels are at the maximum values of 250 v and 20 a. k v and k i are needed to determine the appropriate ratios of the voltage/current transformers and/or shunt resistor values to use in the front-end voltage/cur- rent sensor networks. for a sinewave, the largest rms value that can be accurately measured (wit hout over-driving the in- puts) will register ~0.7071 of the maximum dc in- put level. since power signals are often not perfectly sinusoidal in r eal-world situations, and to provide for some over-range capability, the rms voltage register and rms current register is set to measure 0.6 when the rms-values of the line-voltage and line-current levels are 250 v and 20 a. therefore, when the rms registers measure 0.6, the voltage level at the inputs will be 0.6 x 250 mv = 150 mv. the sensor gain con- stants, k v and k i , are determined by demanding that the voltage and current channel inputs should be 150 mv rms when the power line voltage and current are at the maximum values of 250 v and 20 a. k v = 150 mv / 250 v = 0.0006 k i = 150 mv / 20 a = 0.0075 ? these sensor gain constants are used to calculate what the input voltage levels will be on the CS5460A inputs when the line-voltage and line-current are 220 v and 15 a. these values are v vnom and v inom. v vnom =k v * 220 v = 132 mv v inom =k i * 15 a = 112.5 mv the pulse rate on eout will be at ?pr? pulses per second (hz) when the rms-levels of voltage/cur- rent inputs are at 250 mv. when the voltage/cur- rent inputs are set at v vnom and v inom , the pulse rate needs to be ?ir? = 100 pulses per second. ir will be some percentage of pr. the percentage is defined by the ratios of v vnom /250 mv and v inom /250 mv with the following formula: from this equation the value of ?pr? is shown as:. therefore the pulse-rate register is set to ~420.875 hz, or 0x00349c. the above equation is valid when current channel is set to x10 gain. if current channel gain is set to x50, then the equation becomes: pulserate ir pr v vnom 250mv ------------------- v inom 250mv ------------------- ?? == pr ir v vnom 250mv ------------------ v inom 250mv ------------------ ------------------------------------------- - 100hz 132mv 250mv ------------------ 112.5mv 250mv ---------------------- - ------------------------------------------------ == pr ir v vnom 250mv ------------------ v inom 50mv --------------- ---------------------------------------- - =
CS5460A 22 ds487f4 example #2: the required number of pulses per unit energy present at eout is specified to be 500 pulses/kw-hr; given that the maximum line-voltage is 250 v (rms) and the maximum line-current is 20 a (rms). in such a situation, the nominal line voltage and current do not determine the appropriate pulse-rate setting. instead, the maximum line levels must be considered. as be- fore, the given maximum line-voltage and line-cur- rent levels are used to determine k v and k i : k v = 150 mv / 250 v = 0.0006 k i =150mv/20a=0.0075 ? again the sensor gains are calculated such that the maximum line-voltage and line-current levels will measure as 0.6 in the rms voltage register and rms current register. the required pulse-rate register setting is now determined by using the following equation: therefore pr = ~1.929 hz. note that the pulse-rate register cannot be set to a frequency of exactly 1.929 hz. the closest set- ting that the pulse-rate register can obtain is 0x00003e = 1.9375 hz. to improve the accuracy, either gain register can be programmed to correct for the round-off error in pr. this value would be calculated as in the last example, suppose a value for mclk/k of 3.05856 mhz. when mclk/k is not equal to 4.096 mhz, the result for ?pr? that is calculated for the pulse-rate register must be scaled by a cor- rection factor of: 4.096 mhz / (mclk/k). in this case the result is scaled by 4.096/3.05856 to get a final pr result of ~2.583 hz. 3.2 pulse output for normal format, stepper motor format and mechanical counter format the duration and shape of the pulse outputs at the eout and edir pins can be set for three different output formats. the default setting is for normal output pulse format. when the pulse is set to either of the other two formats, the time duration and/or the relative timing of the eout and edir pulses is increased/varied such that the pulses can drive ei- ther an electro-mechanical counter or a stepper motor. the eout and edir output pins are capa- ble of driving certain low-voltage/low-power counters/stepper motors directly. this depends on the drive current and voltage level requirements of the counter/motor. the ability to set the pulse out- put format to one of the three available formats is controlled by setting certain bits in the control reg- ister. 3.2.1 normal format referring to the description of the control register in section 5., register descriptions , if both the mech and step bits are set to ?0?, the pulse out- put format at the eout and edir pins is illustrated in figure 10. these are active-low pulses with very short duration. the pulse duration is an integer multiple of mclk cycles, approximately equal to 1/16 of the period of the contents of the pulse-rate register. however for pulse-rate register set- tings less than the sampling rate (which is [mclk/8]/1024), the pulse duration will remain at a constant duration, which is equal to the duration of the pulses when the pulse-rate register is set to [mclk/k]/1024. the maximum pulse frequency from the eout pin is therefore [mclk/k]/16. when energy is positive, edir is always high. when energy is negative, edir has the same out- put as eout . when mclk/k is not equal to 4.096 mhz, the true pulse-rate can be found by first calculating what the pulse-rate would be if a 4.096 mhz crystal is used (with k = 1) and then scaling the result by a factor of (mclk/k) / 4.096 mhz. when set to run in normal pulse output format, the pulses may be sent out in ?bursts? depending on both the value of the pulse-rate register as well as the amount of billable energy that was regis- tered by the CS5460A over the most recent a/d sampling period, which is (in hz): 1 / [(mclk/k) / 1024]. a running total of the energy accumulation is maintained in an internal register (not accessible to the user) inside the CS5460A. if the amount of energy that has accumulated in this register over the most recent a/d sampling period is equal to or greater than the amount of energy that is repre- pr 500 pulses kw hr ? ------------------ 1hr 3600s -------------- 1kw 1000w ----------------- - 250mv k v ------------------ 250mv k i ------------------ ?? ? ? = ign or vgn pr 1.929 ------------- 1.00441 ? 0x404830 ==
CS5460A ds487f4 23 sented by one pulse, the CS5460A will issue a ?burst? of one or more pulses on eout (and also possibly on edir ). the CS5460A will issue as many pulses as are necessary to reduce the run- ning energy accumulation value in this register to a value that is less than the energy represented in one pulse. if the amount of energy that has been registered over the most recent sampling period is large enough that it cannot be expressed with only one pulse, then a burst of pulses will be issued, possibly followed by a period of time during which there will be no pulses, until the next a/d sampling period occurs. after the pulse or pulses are issued, a certain residual amount of energy may be left over in this internal energy accumulation register, which is always less (in magnitude) than the amount of energy represented by one pulse. in this situation, the residual energy is not lost or discard- ed, but rather it is maintained and added to the en- ergy that is accumulated during the next a/d conversion cycle. the amount of residual energy that can be left over becomes larger as the pulse-rate register is set to lower and lower val- ues, because lower pulse-rate register values correspond to a higher amount of energy per pulse (for a given calibration). 3.2.2 mechanical counter format setting the mech bit in the control register to ?1? and the step bit to ?0? enables wide-stepping puls- es for mechanical counters and similar discrete counter instruments. in this format, active-low puls- es are 128 ms wide when using a 4.096 mhz crys- tal and k = 1. when energy is positive, the pulses appear on eout . when energy is negative, pulses appear on edir . to insure that pulses will not oc- cur at a rate faster than the 128 ms pulse duration, or faster than the mechanical counter can accom- modate, the pulse-rate register should be set to an appropriate value. because the duration of each pulse is set to 128 ms, the maximum output pulse frequency is limited to ~7.8 hz (for mclk/k = 4.096 mhz). for values of mclk / k different than 4.096 mhz, the duration of one pulse is (128 * 4.096 mhz) / (mclk / k) milliseconds. see figure 11 for a diagram of the typical pulse output. 3.2.3 stepper motor format setting the step bit in the control register to ?1? and the mech bit to ?0? transforms the eout and edir pins into two stepper motor phase outputs. when enough energy has been registered by the CS5460A to register one positive/negative energy eout edir pulse-rate register period 16 n (mclk / k) = for integer n t t 2 = x positive energy burst negative energy burst . . . . . . . . . . . . figure 10. time-plot representation of pulse output for a typical burst of pulses (normal format) 128 ms 128 ms eout edir positive energy negative energy ... ... ... ... figure 11. mechanical counter format on eout and edir
CS5460A 24 ds487f4 pulse, one of the output pins (either eout or edir ) changes state. when the CS5460A must is- sue another energy pulse, the other output chang- es state. the direction the motor will rotate is determined by the order of the state changes. when energy is positive, eout will lead edir such that the eout pulse train wi ll lead the edir pulse train by ~1/4 of the periods of these two pulse train signal. when en ergy is negative, edir will lead eout in a similar manner. see figure 12. 3.3 auto-boot m ode using eeprom the CS5460A has a mode pin. when the mode pin is set to logic low, the CS5460A is in normal op- erating mode, called host mode . this mode de- notes the normal operation of the part, that has been described so far. but when this pin is set to logic high, the CS5460A auto-boot mode is en- abled. in auto-boot mode, the CS5460A is config- ured to request a memory download from an external serial eeprom. the download sequence is initiated by driving the reset pin to logic high. auto-boot mode allows the CS5460A to operate without the need for a microcontroller. note that if the mode pin is left unconnected, it will default to logic low because of an internal pull-down on the pin. 3.3.1 auto-boot configuration figure 13 shows the typical connections between the CS5460A and a serial eeprom for proper au- to-boot operation. in this mode, cs and sclk are driven outputs. sdo is always an output. during the auto-boot sequence, the CS5460A drives cs low, provides a clock output on sclk, and drives out-commands on sdo. it receives the eeprom data on sdi. the serial eeprom must be pro- grammed with the user-specified commands and register data that will be used by the CS5460A to change any of the default register values (if de- sired) and begin conversions. figure 13 also shows the external connections that would be made to a calibrator device, such as a pc eout edir positive energy negative energy ... ... ... ... figure 12. stepper motor format on eout and edir CS5460A eeprom /eout /edir mode sck sdi sdo /cs sck so si /cs connector to calibrator vd+ 5 k 5 k mech. counter stepper motor or figure 13. typical interface of eeprom to CS5460A
CS5460A ds487f4 25 or custom calibration board. when the metering system is installed, the calibrator would be used to control calibration and/or to program user-speci- fied commands and calibration values into the ee- prom. the commands/data will determine the CS5460A?s exact operation, when the auto-boot initialization sequence is running. any of the valid commands can be used. 3.3.2 auto-boot data for eeprom this section illustrates what a typical set of code would look like for an aut o-boot sequence. this code is what would be wri tten into the eeprom. in the sequence below, the eeprom is programmed so that it will first send out commands that write cal- ibration values to the calibration registers inside the CS5460A. this is followed by the commands used to set (write) the desired pulse-rate register value, and also to un-mask the ?lsd? status bit in the mask register. final ly, the eeprom code will initiate ?continuous computation cycles? data acqui- sition mode and select one of the alternate pulse-output formats (e.g., set the mech bit in the control register). the serial data for such a se- quence is shown below in single-byte hexidecimal notation: 40 00 00 61 ;write to configuration regis- ter, turn high-pass filters on, set k = 1. 44 7f c4 a9 ;write value of 0x7fc4a9 to current channel gain regis- ter. 46 7f b2 53 ;write value of 0x7fb253 to voltage channel dc offset register. 4c 00 00 14 ;set pulse rate register to 0.625 hz. 74 00 00 04 ;unmask bit #2 (?lsd? bit in the mask register). e8 ;start performing continuous computation cycles. 78 00 01 40 ;write stop bit to control register, to terminate au- to-boot initialization se- quence, and also set the eout pulse output to me- chanical counter format. this data from the eeprom will drive the sdi pin of the CS5460A during the auto-boot sequence. the following sequence of events will cause the CS5460A to execute the auto-boot mode initializa- tion sequence: (a simple timing diagram for this se- quence is shown below in figure 14.) if the mode pin is set to logic high (or if the mode pin was set/tied to logic high during/after the CS5460A has been powered on), then changing the reset pin from active state to inactive state (low to high) will cause the CS5460A to drive the cs pin low, and af- ter this, to issue the standard eeprom block-read command on the CS5460A?s sdo line. once these events have completed, the CS5460A will continue to issue sclk pulses, to accept data/commands from the eeprom. the serial port will become a master -mode interface. for a more detailed timing diagram, see switching characteristics (in section 1 .) res cs sclk sdo sdi ee read address 0 5460a commands stop mode figure 14. timing diagram for auto-boot sequence
CS5460A 26 ds487f4 3.3.3 application note an225 for more information on auto-boot mode, see the an225 , ?using the CS5460A auto-boot mode?. 3.4 interrupt and watchdog timer 3.4.1 interrupt the int pin is used to indicate that an event has taken place in the CS5460A that (may) need atten- tion. these events inform the meter system about operation conditions and internal error conditions. the int signal is created by combining the status register with the mask register. whenever a bit in the status register becomes active, and the corre- sponding bit in the mask register is a logic 1, the int signal becomes active. 3.4.1.1 clearing t he status register unlike the other registers, the bits in the status register can only be cleared (set to logic 0). when a word is written to the status register, any 1s in the word will cause the corresponding bits in the status register to be cleared. the other bits of the status register remain unchanged. this allows the clearing of particular bits in the register without having to know the state of the other bits. this mechanism is designed to facilitate handshaking and to minimize the risk of losing events that ha- ven?t been processed yet. 3.4.1.2 typical use of the int pin the steps below show how interrupts can be han- dled by the on-board mcu. ? initialization : step i0 - all status bits are cleared by writing ffffff (hex) into the status register. step i1 - the conditional bits which will be used to generate interrupts are then written to logic 1 in the mask register. step i2 - enable interrupts. ? interrupt handler routine : step h0 - read the status register. step h1 - disable all interrupts. step h2 - branch to the proper interrupt service routine. step h3 - clear the status register by writing back the value read in step h0. step h4 - re-enable interrupts. step h5 - return from interrupt service routine. this handshaking procedure insures that any new interrupts activated between steps h0 and h3 are not lost (cleared) by step h3. 3.4.1.3 int active state the behavior of the int pin is controlled by the si1 and si0 bits of the configuration register. the pin can be active low (default), active high, active on a return to logic 0 (pulse-low), or active on a return to logic 1 (pulse-high). if the interrupt output signal format is set for either active-high or active-low assertion, the interrupt condition is cleared when the bits of the status register are returned to their inactive state. if the interrupt output signal format is set for either pulse-high or pulse-low, note that the duration of the int pulse will be at leas t one mclk/k cycle, al- though in some cases the pulse may last for 2 mclk/k cycles. 3.4.1.4 exceptions the ic (invalid command) bit of the status regis- ter can only be cleared by performing the port ini- tialization sequence. this is also the only status register bit that is active low. to properly clear the wdt (watch dog timer) bit of the status register, first read the energy regis- ter, then clear the bit in the status register. 3.4.2 watch dog timer the watch dog timer (wdt) is provided as a means of alerting the system that there is a poten- tial breakdown in communication with the micro- controller. by allowing the wdt to cause an interrupt, a controller can be brought back, from some unknown code space, into the proper code for processing the data created by the converter. the time-out is preprogrammed to approximately 5 seconds. the countdown restarts each time the energy register is read. under typical situations, the energy register is read every second. as a re- sult, the wdt will not time out. other applications that use the watchdog timer will need to ensure
CS5460A ds487f4 27 that the energy register is read at least once in ev- ery 5 second span. 3.5 oscillator characteristics xin and xout are the input and output, respec- tively, of an inverting amplifier to provide oscillation and can be configured as an on-chip oscillator, as shown in figure 15. the oscillator circuit is de- signed to work with a quartz crystal or a ceramic resonator. to reduce circui t cost, two load capaci- tors c1 are integrated in the device, one between xin and dgnd, one between xout and dgnd. lead lengths should be minimized to reduce stray capacitance. to drive the device from an external clock source, xout should be left unconnected while xin is driven by the external circ uitry. there is an amplifi- er between xin and the digital section which pro- vides cmos level signals. this amplifier works with sinusoidal inputs so there are no problems with slow edge times. the CS5460A can be driven by a clock ranging from 2.5 to 20 mhz. the k divider must be set to the appropriate value such that mclk/k will be be- tween 2.5 mhz and 5 mhz. the k divider value is set with the k[3:0] bits in the configuration regis- ter. as an example, if xin = mclk = 15 mhz, and k is set to 5, then mclk/k = 3 mhz, which is a val- id value for mclk/k. note that if the k[3:0] bits are all set to zero, the value of the k divider value is 16. 3.6 analog inputs the CS5460A accommodates a full-scale differen- tial input voltage range of 250 mv on both input channels. (if the pga setting on the current chan- nel is set for the 50x gain setting instead of the 10x gain setting, then the differential full-scale input range on the current channel reduces to 50 mv. ) system calibration can be used to increase or de- crease the full scale span of the converter as long as the calibration register values stay within the limits specified. see section 3.8, calibration , for more details. 3.7 voltage reference the CS5460A is specified for operation with a +2.5 v reference between the vrefin and va- pins. a reference voltage must be supplied to the vrefin pin for proper operation of the two adcs. the CS5460A includes an internal 2.5 v reference, available on the vrefout pin, that can be used as the reference input voltage by connecting the vrefout pin to the vrefin pin. if lower temper- ature drift is desired, an external reference can be used; in which case the vrefout pin should be left unconnected. 3.8 calibration 3.8.1 overview of calibration process the CS5460A offers digital calibration. each cali- bration sequence will be executed by setting/clear- ing one or more of the 8 bits in the calibration command word. for both channels, there are cal- ibration sequences for both ac and dc purposes. regardless of whether an ac or dc calibration se- quence is desired, there are two basic types of cal- ibrations: system offset and system gain. during the calibration sequences, proper input calibra- tion signals to the ?+? and ?-? pins of the volt- age-/current-channel inputs must be supplied. these input calibration signals represent full-scale levels (for gain calibrations) and ground input levels (for offset calibrations). the ac and dc calibration sequences are differ- ent. depending on the specific metering applica- tion and accuracy requirements, some or all of the calibration sequences may not be executed. (this oscillator circuit dgnd xin xout c1 c1 = 22 pf c2 c2 = figure 15. oscillator connection
CS5460A 28 ds487f4 is explained in more detail in the following para- graphs). 3.8.2 the calibration registers refer to figure 3 and figure 21. voltage channel dc offset register and cur- rent channel dc offset register - store additive correction values that are used to correct for dc offsets which may be present on the voltage/cur- rent channels within the entire meter system. these registers are updated by the CS5460A after a dc offset calibration sequence has been execut- ed. voltage channel gain register and current channel gain register - store the multiplicative correction values determined by the full-scale gain calibration signals that are applied to the meter?s voltage/current channels. these registers are up- dated by the CS5460A after either an ac or dc gain calibration sequence has been executed. voltage channel ac offset register and cur- rent channel ac offset register - store additive offset correction values that are used to correct for ac offsets which may be created on the volt- age/current channels within the entire meter sys- tem. although a noise signal may have an average value of zero [no dc offset] the noise may still have a non-zero rms value, which can add an undesir- able offset in the CS5460A?s irms and vrms re- sults. these registers are updated by the CS5460A after an ac offset calibration sequence has been executed. referring to figure 3, one should note that the ac offset registers affect the output results differently than the dc offset registers. the dc offset values are applied to the voltage/current signals very early in the signal path; the dc offset register value af- fects all CS5460A results. this is not true for the ac offset correction. the ac offset registers only affect the results of the rms-voltage/rms-current calculations. referring to figure 3, the reader should note that there are separate calibration registers for the ac and dc offset corrections (for each channel). this is not true for gain corrections, as there is only one gain register per channel--ac and dc gain calibra- tion results are stored in the same register. the re- sults in the gain registers reflect either the ac or dc gain calibration results, whichever was per- formed most recently. therefore, both a dc and ac offset can be applied to a channel at the same time, but only one gain calibration can be applied to each channel. either ac or dc gain calibration can be used, but not both. for both the voltage channel and the current chan- nel, while the ac offset calibration sequence per- forms an entirely different function than the dc offset calibration sequence, the ac gain and dc gain calibration sequences perform the same func- tion (but they accomplish the function using differ- ent techniques). since both the voltage and current channels have separate offset and gain registers associated with them, system offset or system gain can be per- formed on either channel without the calibration results from one channel affecting the other. 3.8.3 calibration sequence 1. the CS5460A must be operating in its active state, and ready to accept valid commands via the spi interface, before a calibration sequence can be executed. clearing the ?drdy? bit in the status register is also recommended. 2. apply appropriate calibration signal(s) to the ?+? and ?-? signals of the voltage/current channel input pairs. (the appropriate calibration signals for each type of calibration sequ ence are discussed next, in sections 3.8.4 and 3.8.5.). the recommended se- quence of calibration, if both gain and offset cali- bration are required, is to run offset calibration before gain calibration; and if both ac and dc off- set calibration are required, dc offset should be calibrated first. 3. next send the 8-bit calibration command to the CS5460A serial interface. 4. after the CS5460A has finished running the de- sired internal calibration sequence and has stored the updated calibration results in the appropriate calibration register s, the drdy bit is set in the sta- tus register to indicate that the calibration se- quence has been completed. if desired, the results of the calibration can now be read from the appro- priate gain/offset registers, via the serial port.
CS5460A ds487f4 29 note that when the calibration command is sent to the CS5460A, the device must not be performing a/d conversions (in either of the two acquisitions modes). if the CS5460A is running a/d conver- sions/computations in the ?continuous computation cycles? acquisition mode (c = 1), the pow- er-up/halt command must be issued first to termi- nate a/d conversions/c omputations. if the CS5460A is running a/d conversions/computa- tions in the ?single comput ation cycle? data acquisi- tion mode (c = 0), the power-up/halt command must be issued first (unless the computation cycle has completed) before executing any calibration sequence. the calibration sequences will not run if the CS5460A is running in either of the two avail- able acquisition modes. 3.8.4 calibration signal input level for both the voltage and current channels, the dif- ferential voltage levels of the calibration signals must be within the specified voltage input limits (re- fer to ?differential input voltage range? in section 1., characteristics & specifications ). for the volt- age channel the peak differential voltage level can never be more than 500 mv p-p . the same is true for the current channel if the current channel input pga is set for 10x gain. if the the current channel?s pga gain is set to 50x, then the current channel?s input limits are 1 00 mv p-p . note that for the ac/dc gain calibrations, there is an absolute limit on the rms/dc voltage levels (re- spectively) that are selected for the voltage/current channel gain calibration input signals. the maxi- mum value that the gain register can attain is 4. therefore, for either channel, if the voltage level of a gain calibration input signal is low enough that it causes the CS5460A to attempt to set either gain register higher than 4, the gain calibration result will be invalid, and after this occurs, all CS5460A results obtained when the part is running a/d con- versions will be invalid. 3.8.5 calibration signal frequency the frequency of the calibration signals must be less than 1 khz (assume mclk/k = 4.096 mhz and k = 1). optimally, the frequency of the calibra- tion signal will be at the same frequency as the fun- damental power line frequency of the power system that is to be metered. 3.8.6 input configur ations for calibrations figure 16 shows the basic setup for gain calibra- tion. if a dc gain calibration is desired, a positive dc voltage level must be applied, such that it truly represents the absolute maximum peak instanta- neous voltage level that needs to be measured across the inputs (inc luding the maximum over-range level that must be accurately mea- sured). in other words, the input signal must be a positive dc voltage level that represents the de- sired absolute peak full-scale value. however, in many practical power metering situations, an ac signal is preferred over a dc signal to calibrate the gain. to perform ac gain calibration instead of dc, an ac reference signal should be applied that is set to the desired maximum rms level. because the voltage/current waveforms that must be mea- sured in most power systems are approximately si- nusoidal in nature, the rms levels of the ac gain calibration input signals may need to be set signif- icantly lower than the voltage/current channel?s maximum dc voltage input level. this must be done in order to avoid the possibility that the peak values of the ac waveforms that are to be mea- sured will not register a value that would be outside the available output code range of the voltage/cur- rent a/d converters. for example, on the voltage channel, if the voltage channel gain register is set to it?s default power-on value of 1.000... before calibration, then the largest pure sinusoidal wave- form that can be used in ac calibration is one whose rms-value is ~0.7071 of the value of the voltage channel?s peak dc input voltage value of 500 mv p-p . thus the maximum value of the input sinusoid would be ~176.78 mv (rms). but in many practical power metering situations, the rms volt- age input level of the ac gain calibration signal may be reduced even further, to allow for some over-ranging capability. a typical sinusoidal cali- bration value which allows for reasonable over-range margin would be 0.6 of the voltage/cur- rent channel?s maximum input voltage level. for the voltage channel, such a sine-wave would have a value of 0.6 x 250 mv rms =150mv rms . for the offset calibrations, there is no difference between the ac and dc calibration signals that must be supplied: simply connect the ?+? and ?-?
CS5460A 30 ds487f4 pins of the voltage/current channels to their ground reference level. (see figure 17.) offset and gain calibration cannot be done at the same time. this will cause undesirable calibration results. 3.8.7 description of calibration algo- rithms the computational flow of the CS5460A?s ac and dc gain/offset calibration sequences are illustrat- ed in figure 18. this figure applies to both the volt- age channel and the current channel. the following descriptions of calibration sequences will focus on the voltage channel, but apply equally to the current channel. note: for proper calibration, it is assumed that the value of the voltage-/current-channel gain registers are set to default (1.0) before running the gain calibration(s), and the value in the voltage-/current channel ac and dc offset registers is set to default (0) before running calibrations. this can be accomplished by a software or hardware reset of the device. the values in the voltage/curr ent calibration registers do affect the results of the calibration sequences. 3.8.7.1 ac offset calibration sequence the idea of the ac offset calibration is to obtain an offset value that reflects the square of the rms output level when the inputs are grounded. during normal operation, when the CS5460A is calculat- ing the latest result for the rms voltage register, this ac offset register value will be subtracted from the square of each successive voltage sample in order to nullify the ac offset that may be inherent in the voltage-channel signal path. note that the value in the ac offset register is proportional to the square of the ac offset. first, the inputs are grounded, and then the ac off- set calibration command is sent to the CS5460A. when the ac offset calibration sequence is initiat- ed, a valid rms voltage register value is acquired and squared. this value is then subtracted from the square of each voltage sample that comes through the rms data path. see figure 18. + - xgain + - external connections + - ain+ ain- cm + - full scale (dc or ac) figure 16. system calibration of gain. + - xgain + - external connections 0v + - ain+ ain- cm + - figure 17. system calibration of offset. in modulator + x to v*, i*, p*, e* registers filter n v rms n sinc dc offset* gain* + x 2 -x 1 x n ac offset* x 2 0.6 x + + - + 2 * * denotes readable/writable register x n figure 18. calibration data flow
CS5460A ds487f4 31 3.8.7.2 dc offset calibration sequence the voltage channel dc offset register holds the negative of the simple average of n samples taken while the dc voltage offset calibration was execut- ed. the inputs should be grounded during dc off- set calibration. the dc offset value is added to the signal path to nullify the dc offset in the system. 3.8.7.3 ac gain calibration sequence the ac voltage gain calibration algorithm attempts to adjust the voltage channel gain register value such that the calibration reference signal level pre- sented at the voltage inputs will result in a value of 0.6 in the rms voltage register. the ac calibra- tion signal is applied to t he ?+? and ?-? input pins of the channel under calibration. during ac voltage gain calibration, the value in the rms voltage reg- ister is divided into 0.6. this result is the ac gain calibration value stored in the voltage channel gain register. 3.8.7.4 dc gain calibration sequence based on the level of the positive dc calibration voltage that should be applied across the ?+? and ?-? inputs, the CS5460A det ermines the voltage channel gain register value by averaging the in- stantaneous voltage register?s output signal val- ues over one computation cycle (n samples) and then dividing this average into 1. therefore, after the dc voltage gain calibration has been executed, the instantaneous voltage register will read full-scale whenever the dc level of the input signal is equal to the level of the dc calibration signal that was applied to the voltage channel inputs during the dc gain calibration. for example, if a +230 mv dc signal is applied to the voltage channel inputs during the dc gain calibration for the current chan- nel, then the instantaneous voltage register will measure unity whenever a 230 mv dc level is ap- plied to the voltage channel inputs. 3.8.8 duration of calibration sequence the value of the cycle count register (n) deter- mines the number of conversions that will be per- formed by the CS5460A duri ng a given calibration sequence. for dc offset/gain calibrations, the cal- ibration sequence always takes at least n + 30 conversion cycles to complete. for ac offset/gain calibrations, the calibration sequence takes at least 6n + 30 a/d conversion cycles to complete, (about 6 computation cycles). if n is increased, the accuracy of calibration results will increase. for more information on calibration, see an227 , ?calibrating the CS5460A?. 3.9 phase compensation the values of bits 23 to 17 in the configuration register can be altered to adjust the amount of time delay that is imposed on the digitally sampled voltage channel signal. this time delay is applied to the voltage channel signal in order to compen- sate for the relative phase delay (with respect to the fundamental frequency) between the sensed voltage and current signals. voltage and current transformers, as well as other sensor/filter/protec- tion devices deployed at the front-end of the volt- age/current sensor networks can often introduce a phase-delay in the system that distorts/corrupts the phase relationship between the line-voltage and line-current signals that are to be measured. the phase compensation bits pc[6:0] in the con- figuration register can be set to nullify this undesir- able phase distortion between the digitally sampled signals in the two channels. the value in the 7-bit phase compensation word indicates the amount of time delay that is imposed on the volt- v rms register = 230 / 250 x 1 / 2 0.65054 250 mv 230 mv 0 v -230 mv -250 mv 0.9999... 0.92 -0.92 -1.0000... v rms register = 0.6000... 250 mv 230 mv 0 v -230 mv -250 mv 0.84853 -0.84853 before ac gain calibration (vgain register = 1) after ac gain calibration (vgain register changed to ~0.9223) instantaneous voltage register values instantaneous voltage register values sinewave sinewave 0.92231 -0.92231 input signal input signal figure 19. example of ac gain calibration
CS5460A 32 ds487f4 age channel?s analog input signal with respect to the current channel?s analog input signal. with the default setting, the phase delay on the voltage channel signal is ~0.995 s (~0.0215 de- grees assuming a 60 hz power signal). with mclk = 4.096 mhz and k = 1, the range of the in- ternal phase compensation ranges from -2.8 degrees to +2.8 degrees when the input volt- age/current signals are at 60 hz. in this condition, each step of the phase com pensation register (val- ue of one lsb) is ~0.04 degrees. for values of mclk other than 4.096 mhz, these values for the span (-2.8 to +2.8 degrees) and for the step size (0.04 degrees) should be scaled by 4.096 mhz / (mclk / k). for power line frequen- cies other than 60hz (e.g., 50 hz), the values of the range and step size of the pc[6:0] bits can be determined by converting the above values to time-domain (seconds), and then computing the new range and step size (in degrees) with respect to the new line frequency. unlike offset/gain calibration, the CS5460A does not provide an automated on-chip phase calibra- tion sequence. to calibrate the phase delay, the phase compensation bits can be adjusted while the CS5460A is running in ?continuous computation cycles? data acquisition mode. for example, the CS5460A can be set up to perform continuous computations on a purely resistive load (no induc- tance or capacitance). the pc[6:0] bits can then be adjusted until the energy register value is max- imized. 3.10 time-base calibration register the time-base calibration register (notated as ?tbc? in figure 3) is used to compensate for slight errors in the xin input frequency. external oscilla- tors and crystals have certain tolerances. if there is a concern about improving the accuracy of the clock for energy measurements, the time-base calibration register value can be manipulated to compensate for the frequency error. note from fig- ure 3 that the tbc register only affects the value in the energy register. as an example, if the desired xin frequency is 4.096 mhz, but during production-level testing, suppose that the average frequency of the crystal on a particular board is measured to actually be 4.091 mhz. the ratio of the desired frequency to the actual frequency is 4.096 mhz/4.091 mhz = ~1.00122219506. the tbc register can be set to 1.00122213364 = 0x80280c(h), which is very close to the desired ratio. 3.11 power offset register referring to figure 3, note the ?p off ? register that appears just after the power computation. this reg- ister can be used to offset system power sources that may be resident in the system, but do not orig- inate from the power line signal. these sources of extra energy in the system contribute undesirable and false offsets to the power/energy measure- ment results. for example, even after dc offset and ac offset calibrations have been run on each channel, when a voltage signal is applied to the voltage channel inputs and the current channel is grounded (i.e., there is zero input on the current channel), the current channel may still register a very small amount of rms current caused by leak- age of the voltage channel input signal into the cur- rent channel input signal path. although the CS5460A has high channel-to-channel crosstalk rejection, such crosstalk may not totally be elimi- nated.) if the amount of ?artificial? power that might be induced into the voltage/current channel signals due to such crosstalk/system noise/etc. can be de- termined, then the power offset register can be programmed to nullify the effects of this unwanted energy. 3.12 input protecti on - current limit in figures 6, 7, 8, and 9, note the series resistor r i+ which is connected to the iin+ input pin. this resis- tor serves two purposes. first, this resistor func- tions in coordination with c idiff and/or c idiff to form a low-pass filter. the filter will a) remove any broad- band noise that is far outside of the frequency range of interest, and also b) this filter serves as the anti-aliasing filter , which is necessary to pre- vent the a/d converter from receiving input signals whose frequency is higher than one-half of the sampling frequency (the nyquist frequency). the second purpose of this resistor is to provide cur- rent-limit protection for the iin+ input pin, in the event of a power surge or lightning surge. the role that r i+ contributes to input filtering will be dis- cussed in the section 3.13. but first the current-lim- it protection requirements for the iin+/iin- and vin+/vin- pins are discussed.
CS5460A ds487f4 33 the voltage/current-channel inputs have surge-current limits of 100 ma. this applies to brief voltage/current spikes (<250 ms). the limit is 10 ma for dc input overload situations. to prevent permanent damage to the CS5460A, the designer must include adequate protection circuitry in the power meter design, to insure that these pin cur- rent limits are never exceeded, when CS5460A is operating in the intended power-line metering envi- ronment. focusing specifically on figure 7, which shows how voltage/current transformers can be used to sense the line-voltage/line-current, suppose for ex- ample that the requirements for a certain 120 vac power system require that the power meter must be able to withstand up to a 8 kv voltage spike on the power line during normal operating conditions. to provide a suitable sensor voltage input level to the voltage channel input pins of the CS5460A, the turns ratio of the voltage-sense transformer should be chosen such that the ratio is, for example, on the order of 1000:1. a voltage-sense transformer with a 1000:1 turns ratio will provide a 120 mv (rms) signal to the CS5460A?s differential voltage channel inputs, when the power line voltage is at the nominal level of 120 vac. therefore, a brief 8 kv surge would be reduced to a 8 v surge across r v+ . what happens when 8 volts (common-mode) is present across one of the analog input pins of the CS5460A? the vin+/vin- and iin+/iin- pins of the CS5460A are equipped with internal protection di- odes. if a voltage is presented to any of these pins that is larger than approximately 7 v (with respect to va- pin) these protection diodes will turn on in- side the CS5460A. but in order to prevent exces- sive current levels from flowing through the device, the value of r v+ must be large enough that when a 8v surge is present across the secondaries of the voltage-sense transformer, the brief surge current through r v+ should not be any greater than 100 ma. therefore, a minimum value for r v+ would be (8 v - 7 v) / 100 ma = 10 ? . this value may be increased as needed, to easily obtain the desired cutoff frequency of the anti-aliasing filter on the voltage channel (described later), and also to provide some margin. but the designer should try to avoid using values fo r the protection resistors that are excessively high. a typical value for r v+ would be 470 ? . the vin- pin should also have a protection resistor (called r v- in figure 7). to maintain symmetry, the value of r v- should be made equal to r v+ . for the current channel inputs (iin+ and iin-), if the maximum current rating (i max ) for this power line is 30 a (rms), then a suitable turns ratio for the cur- rent-sense transformer might be 200:1. since the maximum load for a 120 vac line rated at 30 a would be 4 ? (for unity power factor), a brief 8 kv surge across ?l? and ?n? could generate as much as 2000 a (rms) of current through the primaries of the current-sense transformer. this can in turn generate as much as 10 v across the secondaries of the current-sense transformer. this voltage is high enough to turn on one or more of the internal protection diodes located off of the iin+/iin- pins. therefore, the value of the protection resistor that will limit the current flow to less than 100 ma would be (10 v - 7 v) / 100 ma = 30 ? . in order to pro- vide some margin and to use the same resistor val- ues that are used on the vin+/vin- pins, a 470 ? resistor can be used as a lower limit for the r i+ and r i- resistors shown in figure 7. referring to the circuit implementations shown in figures 6, 8, and 9, note that when resistor-divider configurations are used to provide the voltage channel sense voltage, the vin+ pin does not need an additional, separate, dedicated protection resis- tor. this is because the resistive voltage-divider al- ready provides the series resistance that is needed for this protection resistance (from r 1 and r 2 ). (and note in figure 8 that this is true for both the vin+ pin and the vin- pin.) in figure 7, a voltage transformer is used as the voltage sensor. when any type of transformer is used as the sensor de- vice for voltage (or current) channel, a dedicated protection resistor r v+ should be installed in series with the vin+ pin, and similarly, a resistor (r v- ) should be installed in series to the vin- input pin. additional considerati ons/techniques regarding the protection of the analog input pins against sud- den high-frequency, high-level voltage/current surges are discussed in section 3.14.
CS5460A 34 ds487f4 3.13 input filtering figure 6 shows how the analog inputs can be con- nected for a single-ended input configuration. note here that the vin- and iin- input pins are held at a constant dc common-mode level, and the varia- tion of the differential input signal occurs only on the vin+ and vin- pins. the common-mode level on the vin-/iin- pins is often set at (or very near) the CS5460A?s common-mode ground reference po- tential. (the common-mode ground reference po- tential is defined by the voltage at the va- pin.) but this is not required--the dc reference level of the vin-/iin- pins can be set to any potential be- tween [va-] and [(va+) - 250 mv]. in figure 6, ob- serve the circuitry which has been placed in front of the current channel input pins, as one example. the anti-aliasing filter can be constructed by calcu- lating appropriate values for r i+ =r i- , c idiff , and c i+ = c i- . the sensor voltage that is created by the voltage drop across r shunt is fed into the iin+ pin, while the voltage at the iin- pin is held constant. figure 7 shows a differential bipolar input configu- ration. note in figure 7 that the ?+? and ?-? input pins for the voltage/current channels are equally referenced above and below the CS5460A?s ground reference voltage. such a differential bipo- lar input configuration can be used because the CS5460A voltage/current channel inputs are able to accept input voltage levels as low as -250 mv (common-mode) below the va- pin ground refer- ence, which is defined by the voltage at the va- pin. (in fact, if desired, the center-tapped reference of these differential input pairs could be connected to a dc voltage of, for example, +2 v, because +2 v is within the available common-mode range of [va-] and [va+ - 250mv]. but this configuration may not be practical for most metering applica- tions.) in the differential bipolar input configuration, the voltage signals at the vin- and iin- pins will fluc- tuate in similar fashion to the vin+/iin+ pins, except the voltages at the ?-? pins will be 180 degrees out of phase with respect to the voltage signals at the ?+? pins. therefore the signal paths to the ?+? and ?-? pins play an equal role in defining the differential voltage input signal. because of this, the protection resistors placed on vin-/iin- pins will play an equal- ly important role as the resistors on the vin+/iin+ pins, in defining the differential responses of the voltage/current channel input anti-aliasing filters. these resistors also serve as the current-limit pro- tection resistors (mentioned earlier). before determining a typical set of values for r v+ , r v- , c v+ , c v- , c vdiff , r i+ , r i- , c i+ , c i- , and c idiff in figure 7, several other factors should be consid- ered: 1. values for the above resistors/capacitors should be chosen with the desired differential-mode (and common-mode) lowpass cutoff frequencies in mind. in general, the differential cutoff frequencies should not be less than 10 times the cut-off fre- quencies of the internal voltage/current channel fil- ters, which can be estimated by studying figure 4 and figure 5. in these figures, the internal voltage channel cutoff frequency is ~1400 hz while the current channel cutoff frequency is ~1600 hz. if the cutoff frequency of the external anti-aliasing fil- ter is much less than 10x these values (14000 hz and 16000 hz), then some of the harmonic content that may be present in the voltage/current signals will be attenuated by the voltage/current channel input anti-aliasing filters, because such r-c filters will begin to roll off at a frequency of 1/10th of the filter?s -3 db cutoff frequency. if the designer is not interested in metering energy that may be present in the higher harmonics (with respect to the funda- mental power line frequency) then the differen- tial-mode cutoff frequencies on the voltage/current input networks can be reduced. however, relaxing the metering bandwidth is usually unacceptable, as most modern power meters are required to reg- ister energy out to the 11th harmonic (at a mini- mum). 2. the first-order time-constants of the overall volt- age and current channel sensor networks should be set such that they are equal (within reason), or at least close in magnitude. if the time-constants of the voltage/current sensor networks are not well-matched, then the phase relationship be- tween the voltage-sense and current-sense sig- nals will suffer an undesirable shift. in this situation, the real (true) power/energy measure- ments reported by the CS5460A can contain signif- icant error, because the power factor of the sensed voltage and current signals will be significantly dif- ferent than the actual power factor of the power line voltage/current waveforms.
CS5460A ds487f4 35 note also that in addition to the time-constants of the input r-c filters, the phase-shifting properties of the voltage/current sensors devices may also contribute to the overall time-constants of the volt- age/current input sensor networks. for example, current-sense transformers and potential trans- formers can impose phase-shifts on the sensed current/voltage waveforms. therefore, this possi- ble source of additional phase-shift caused by sen- sor devices may also need to be considered while selecting the final r and c values for the volt- age/current anti-aliasing filters. as an alternative to, or in addition to the fine adjustment of the r and c values of the two anti-alias filters, the CS5460A?s phase compensation bits (see phase compensa- tion ) can also be adjusted, in order to more closely match the overall time-constants of the volt- age/current input networks. regardless of whether the phase compensation bits are or are not used to help more closely match the time-constants, this requirement of equal time-constants must ulti- mately be considered when selecting the final r and c values that will be used for the input filters. (of course, this factor may not turn out to be so im- portant if the designer is confident that the mis-match between the voltage/current channel time-constants will not cause enough error to vio- late the accuracy requirements for the given pow- er/energy metering application.) 3. referring to the specs in section 1 , note that the differential input impedance across the current channel input pins is only 30 k ? , which is signifi- cantly less than the corresponding impedance across the voltage channel input pins (which is 1m ? ). while the impedance across the voltage channel is usually high enough to be ignored, the impedance across the current channel inputs may need to be taken into account by the designer when the desired cutoff frequencies of the filters (and the time-constants of the overall input net- works) are computed. also, because of this rather low input impedance across the current channel in- puts, the designer should note that as the values for r i+ and/or r i- are increased, the interaction of the current channel?s input impedance can begin to cause a significant voltage drop within the current channel input network. if this is not taken into ac- count, values may be chosen for r i+ =r i- that are large enough to cause a discrepancy between the expected (theoretical) sensor gain and the actual sensor gain of the current sensor network, which may not be anticipated by the designer. also, if this voltage drop effect is not considered, the designer may select values for r i+ and r i that are slightly larger than they should be, in terms of maximizing the available dynamic range of the current channel input. for the very same reason, the line-cur- rent-to-sensor-output-voltage conversion factor of the current sensor may not be optimized if this volt- age division is not considered, when (for example) selecting a value for the burden resistor for a given current transformer. this issue should be consid- ered, although a slight voltage drop only causes a slight loss in available dynamic range, and the ef- fects of this voltage drop on the actual current channel sensor gain can be removed during gain calibration of the current channel. 4. referring to figures 6 - 9, not all of the capaci- tors/resistors shown in these example circuit dia- grams are necessary; however, note that the all of the filter capacitors (c v+ , c v- , c i+ , c i- , c vdiff , and c i- diff ) can, in some situations, help to improve the ability of both input networks to attenuate very high-frequency rfi that can enter into the CS5460A?s analog input pins. therefore, during layout of the pcb, these capacitors should be placed in close proximity to their respective input pins. if any/all of the common-mode connected capaci- tors (c v+ , c v- , c i+ , c i- ) are included in the input net- works, their values should be selected such that they are at least one order of magnitude smaller than the value of the differential capacitors (c vdiff , and c idiff ). this is done for at least two reasons: a) the value tolerance for most types of commer- cially available surface- mount capacitors is not small enough to insure appreciable value match- ing, between the value of c v+ vs. c v- , as well as between the value of c v+ vs. c v- . such value mis- match can adversely affect the desired differen- tial-mode response of the voltage/current input networks. by keeping the values of these com- mon-mode capacitors small, and allowing the val- ue of the c vdiff , and c idiff to dominate the differential 1st-order time-constant of the input filter networks, this undesirable possibility of frequency response variation can be minimized.
CS5460A 36 ds487f4 b) the common-mode rejection performance of the CS5460A is sufficient within the frequency range over which the CS5460A performs a/d conver- sions. addition of such common-mode caps can actually often degrade the common-mode rejec- tion performance of the entire voltage/current input networks. therefore, choosing relatively small val- ues for (c v+ , c v- , c i+ , c i- ) will provide necessary common-mode rejection at the much higher fre- quencies, and will allow the CS5460A to realize its cmrr performance in the frequency-range of in- terest. [note that this discussion does not include correc- tion of phase-shifts caused by the voltage-sense transformer and current-sense transformer, al- though these phase-shifts s hould definitely be con- sidered in a real-life practical meter design.] on the current channel, using commonly available values for the components, r i+ and r i- can be set to 470 ? . then a value of c idiff = 18 nf and a value of 0.22 nf for c i- and c i- will yield a -3 db cutoff fre- quency of 15341 hz for the current channel. for the voltage channel, if r i+ and r i- are also set to 470 ? , c vdiff = 18 nf, and c v- =c v- =0.22nf (same as current channel), the -3 db cutoff fre- quency of the voltage channel?s input filter will be 14870 hz. the difference in the two cutoff frequen- cies is due to the difference in the input impedance between the voltage/current channels. if there is concern about the effect that the differ- ence in these two cutoff frequencies (and therefore the mis-match between the time-constants of the overall voltage/current in put networks) would have on the accuracy of the power/energy registration, a non-standard resistor value for r v+ =r v- of (for ex- ample) 455 ? can be used. this would shift the (differential) -3 db cutoff frequency of the voltage channel?s input filter (at the voltage channel inputs) to ~15370 hz, which would cause the first-order time-constants of the voltage/current channel input filters to be closer in value. agreement between the voltage/current channel time-constants can also be obtained by adjusting the phase compensation bits, instead of using less commonly-available resistor/capacitor values (such as r i+ =r i- = 455 ? ). if the values of r i+ and r i- are again 470 ? , the first-order time-constants of the two r-c filters are estimated by taking the re- ciprocal of the -3 db cutoff frequencies (when ex- pressed in rads/s). subtracting these two time-constants shows that after the voltage/current signals pass through their respective anti-aliasing filters, the sensed voltage signal will be delayed ~0.329 s more than the current signal. if metering a 60 hz power system, this implies that the input voltage-sense signal will be delayed ~0.007 degrees more than the delay imposed on the input current-sense signal . note that when the pc[6:0] bits are set to their default setting of ?0000000?, the internal filtering stages of the CS5460A will impose an additional delay on the fundamental frequency component of the 60hz voltage signal of 0.0215 degrees, with respect to the current signal. the total difference between the delay on the voltage-sense fundamental and the current-sense fundamental will therefore be ~0.286 degrees. but if the phase compensation bits are set to 1111111, the CS5460A will delay the voltage channel signal by an additional -0.04 de- grees, which is equivalent to shifting the voltage signal forward by 0.04 degrees. the total phase shift on the voltage-sense signal (with respect to the fundamental frequency) would then be ~0.011 degrees ahead of the current-sense signal, which would therefore provide more close- ly-matched delay values between the volt- age-sense and current-sense signals. adjustment of the pc[6:0] bits therefore can provide an effec- tive way to more closely match the delays of the voltage/current sensor signals, allowing for more commonly available r and c component values to be used in both of these filters. as a final note, tolerances of the r and c compo- nents that are used to build the two r-c filters should also be taken into consideration. a com- mon tolerance of 0.1% can vary the delay by as much as much as ~2.07 s, which means that the difference between the delays of the voltage-sense and current-sense signals that is caused by these filters could vary by as much as ~4.1 s, which is equivalent to a phase shift of ~0.089 degrees (at 60 hz). this in turn implies that our decision to ad- just the pc[6:0] bits (to shift the voltage signal for- ward by 0.04 degrees) could actually cause the voltage signal to be shifted by as much as ~0.100 degrees ahead of the current signal. thus, adjustment of the pc[6:0] bits to more close- ly match the two time-constants/delays may only be useful if a precise calibration operation can be
CS5460A ds487f4 37 performed on each individual power meter, during final calibration/test of the meter. 3.14 protection against high-voltage and/or high-current surges in many power distribution systems, it is very likely that the power lines will occasionally carry brief but large transient spikes of voltage/current. two com- mon sources of such high-energy disturbances are 1) a surge in the line during a lightning storm, or 2) a surge that is caused when a very inductive or ca- pacitive load on the power line is suddenly turned on (?inductive kick?). in these situations, the input protection resistors and corresponding input filter capacitors (discussed in the previous sections) may not be sufficient to protect the CS5460A from such high-frequency voltage/current surges. the surges may still be strong enough to cause perma- nent damage to the CS5460A. because of this, the designer should consider adding certain additional components within the voltage/current channel in- put circuitry, which can help to protect the CS5460A from being permanently damaged by the surges. referring to figure 20, the addition of capacitors c1 and c2 can help to further attenuate these high-frequency power surges, which can greatly decrease the chances that the CS5460A will be damaged. typical values for c1 and c2 may be on the order of 10 pf, although the exact value is re- lated to the reactive and resistive properties of the voltage and current sensor devices. in addition, di- odes d1 - d4 can help to quickly clamp a high volt- age surge voltage presented across the voltage/current inputs, before such a surge can damage the CS5460A. an example of a suitable diode part number for this application is bav199, which has the ability to turn on very quickly (very small turn-on time). a fuse could potentially serve this purpose as well (not shown). r3 and r4 can provide protection on the ?-? sides of the two input pairs. set r3 = r1 and r4 = r5. finally, placing 50 ? resistors in series with the va+ and vd+ pins is another technique that has sometimes proven to be effective in protecting the CS5460A from such high-level, high-frequency voltage/current surges. however, these 50 ? resistors may not be neces- sary if the protection on the analog input channels is sufficient, and this is not the most attractive so- va+ vd+ CS5460A 0.1 f 100 f 500 ? 470 nf 500 ? n 10 ? 14 vin+ 9 vin- iin- 10 15 16 iin+ pfmon cpuclk xout xin reset 17 2 1 24 19 cs 7 sdi 23 sdo 6 sclk 5 int 20 edir 22 eout 21 0.1 f vrefin 12 vrefout 11 va- dgnd 13 4 3 0.1 f 10 k ? 5 k ? l r l 4.069 mhz to service 1 k 1 k 1 k 1 k +5 v +5 v 10 k 10 k 47 k 47 k 20 k 20 k 1 k sclk sdo cs int sdi rst gnd +5 v 5.1 volt 1 k 120 vrms 50 50 for input surge protection to reduce emi susceptibility d1 d2 d4 d3 r3 r4 c1 c2 r1 r2 r shunt r5 c4 c5 c6 c7 c3 c8 mode nc 8 nc l3 l4 l1 l2 figure 20. input protection for single-ended input configurations input protection for single-ended inpu t configurations, using resistive divider and current shunt resistor. note that the digital interface is isolated using opto-isolators.
CS5460A 38 ds487f4 lution, because these resistors will dissipate what can be a significant amount of power, and they will cause an undesirable voltage drop which decreas- es the voltage level presented to the va+ and vd+ supply pins. 3.15 improving rfi immunity during emc acceptance testing of a power meter- ing assembly, the performance of the CS5460A?s a/d converters can be adversely affected by exter- nal radio frequency interference (rfi). such exter- nal rfi can be coupled into the copper traces and/or wires on the pcb. if rfi is coupled into any of the traces which tie into the CS5460A?s vin+/vin- or iin+/iin- input pins, then errors may be present in the CS5460A?s power/energy registra- tion results. when such degradation in performance is detect- ed, the CS5460A?s immunity to rf disturbance may be improved by configuring the ?+? and ?-? in- puts of the voltage/current channel inputs such that they are more symmetrical . this is illustrated in figure 20 with the addition of resistors r3 and r4, as well as capacitors c5 and c6. note that the in- put circuitry placed in front of the voltage/current channel inputs in figure 20 represents a sin- gle-ended input configurations (for both channels). therefore, these extra resistors and components may not necessarily be needed to achieve the sim- ple basic anti-aliasing filtering on the inputs. how- ever, the addition of these extra components can create more symmetry across the ?+? and ?-? inputs of the voltage/current input channels, which can of- ten help to reduce the CS5460A?s susceptibility to rfi. the value of c5 should be the same as c3, (and so the designer may have to re-calculate the desired value of c3, since the addition of c5 will change the overall differ ential-/common-mode fre- quency responses of the input filter.) a similar ar- gument can be made for the addition of c6 (to match c8) on the current channel?s input filter. fi- nally, addition of capacitors c4 and c7 can also sometimes help to improve CS5460A?s perfor- mance in the presence of rf i. all of these input ca- pacitors (c3 - c8) should be placed in very close proximity to the ?+? and ?-? pins of the voltage/cur- rent input pins in order to maximize their ability to protect the input pins from high-frequency rfi. in addition to or as an alternative to these capacitors, addition of inductors l1 - l4 can sometimes help to suppress any incoming rfi. note that the addition- al components just discussed can sometimes actu- ally degrade the CS5460A?s immunity to rfi. the exact configuration that works best can vary signif- icantly, according to the exact pcb layout/orienta- tion. finally, note that inside the CS5460A, the vin+, vin-, iin+, and iin- pi ns have all been buffered with ~10 pf of internal capacitance (to va-) in at- tempt to improve the device?s immunity to external rfi. 3.16 pcb layout for optimal performance, the CS5460A should be placed entirely over an analog ground plane with both the va- and dgnd pins of the device con- nected to the analog plane. note: refer to the cdb5460a evaluation board for suggested layout details, as well as applications note 18 fo r more detailed layout guidelines. before layout, please call for our free schematic review service. 4. serial port overview the CS5460A's serial port incorporates a state machine with transmit/receive buffers. the state machine interprets 8 bit command words on the rising edge of sclk. upon decoding of the com- mand word, the state machine performs the re- quested command or prepares for a data transfer of the addressed register. request for a read re- quires an internal register transfer to the transmit buffer, while a write waits until the completion of 24 sclks before performing a transfer. the inter- nal registers are used to control the adc's func- tions. all registers are 24-bits in length. figure 21, in section 5, summarizes the internal registers available. the CS5460A is initialized and fully operational in its active state upon power-on. after a power-on, the device will wait to receive a valid command (the first 8-bits clocked into the serial port). upon re- ceiving and decoding a valid command word, the state machine instructs the converter to either per- form a system operation, or transfer data to or from an internal register.
CS5460A ds487f4 39 4.1 commands (write only) all command words are 1 byte in length. commands that write to a register must be followed by 3 bytes of register data. commands that read from register s initiate the output of 3 bytes of register data. commands that read data can be ?chained? with other commands (e.g., while reading data, a new command can be sent to sdi which can ex- ecute before the original read is complete d). this allows for ?chaining? commands. 4.1.1 start conversions this command indicates to the state machine to begin acqui ring measurements and calculating results. the device has two modes of acquisition. modes of acquisition/measurement 0 = perform a single computation cycle 1 = perform continuou s computation cycles 4.1.2 sync0 command this command is the end of the serial port re-initialization sequence. it can also be used as a nop command. the serial port is resynchronized to byte boundaries by sending three or more consecutive sync1 commands followed by a sync0 command. 4.1.3 sync1 command this command is part of the serial port re-initi alization sequence. it can also serve as a nop command. 4.1.4 power-up/halt if the device is powered-down into either stand-by or sleep power saving mode (see 4.1.5 ), this command will pow- er-up the device. after the CS5460A is initially powered-on, no conversions/com putations will be r unning. if the de- vice is already powered on and the device is running eith er ?single computation cycle? or ?continuous computation cycles? data acquisition modes, all computations will be halted on ce this command is received. b7 b6 b5 b4 b3 b2 b1 b0 1110c000 b7 b6 b5 b4 b3 b2 b1 b0 11111110 b7 b6 b5 b4 b3 b2 b1 b0 11111111 b7 b6 b5 b4 b3 b2 b1 b0 10100000
CS5460A 40 ds487f4 4.1.5 power-down the device has two power-down st ates to conserve power. if the chip is put in stand-by state, all circuitry except the analog/digital clock generators is turned of f. in the sleep state, all circuitry ex cept the digital clock generator and the instruction decoder is turned off. waking up the CS5460A out of sleep state requires more time than waking the device out of stand-by state, because of the extra time needed to re-start and re-stabiliz e the analog clock signal. [s1 s]0 power-down state 00 = reserved 01 = halt and enter stand-by power saving state. this state allows quick power-on time 10 = halt and enter sleep power saving stat e. this state requires a slow power-on time 11 = reserved 4.1.6 calibration the device has the capability of performing a system ac offset calibration, dc offset calibration, ac gain calibration, and dc gain calibration. calibration can be done on the volt age channel, the current channel, or both channels at the same time. offset and gain calibrations should not be performed at the same time (must do one after the oth- er). for a given application, if dc gain calibrations are per formed, then ac gain calibration should not be performed (and vice-versa). the proper input voltages must be supplied to the device before initiating calibration. [v i] designates calibration channel 00 = not allowed 01 = calibrate th e current channel 10 = calibrate the voltage channel 11 = calibrate voltage and current channel simultaneously r specifies ac calibration (r =1) or dc calibration (r=0) g designates gain calibration 0 = normal operation 1 = perform gain calibration o designates offset calibration 0 = normal operation 1 = perform offset calibration b7 b6 b5 b4 b3 b2 b1 b0 1 0 0s1s00 0 0 b7 b6 b5 b4 b3 b2 b1 b0 110virgo
CS5460A ds487f4 41 4.1.7 register read/write this command informs the state machine that a register access is required. on reads the addressed register is load- ed into the output buffer and clocked out by sclk. on writes the data is clocked into th e input buffer and transferred to the addressed register on the 24 th sclk. w/r write/read control 0 = read register 1 = write register ra[4:0] register address bits. binary encoded 0 to 31. all registers are 24 bits in length. address abbreviation name/description 00000 config configuration register. 00001 i dcoff current channel dc offset register. 00010 i gn current channel gain register. 00011 v dcoff voltage channel dc offset register. 00100 v gn voltage channel gain register. 00101 cycle count number of a/ d cycles per computation cycle. 00110 pulse-rate used to set the energy-to-pulse ratio on eout (and edir ). 00111 i instantaneous current register (most recent current sample). 01000 v instantaneous voltage regist er (most recent voltage sample). 01001 p instantaneous power regist er (most recent power sample). 01010 e energy register (accumulated over latest computation cycle). 01011 i rms rms current register (computed over latest computation cycle). 01100 v rms rms voltage register (computed over latest computation cycle). 01101 tbc timebase calibration register. 01110 poff power offset register. 01111 status status register. 10000 i acoff current channel ac offset register. 10001 v acoff voltage channel ac offset register. 10010 res reserved ? . . . . . . 10111 res reserved ? 11000 res reserved ? 11001 test reserved ? 11010 mask mask register. 11011 res reserved ? 11100 ctrl control register. 11101 res reserved ? . . . . . . 11111 res reserved ? ? these registers are for internal use only and should not be written to. b7 b6 b5 b4 b3 b2 b1 b0 0w/r ra4 ra3 ra2 ra1 ra0 0
CS5460A 42 ds487f4 4.2 serial port interface the CS5460A?s slave-mode serial interface con- sists of two control lines and two data lines, which have the following pin-names: cs , sclk, sdi, sdo. each control line is now described. cs chip select (input pin), is the control line which enables access to the serial port. when cs is set to logic 1, the sdi, sdo, and sclk pins will be held at high impedance. when the cs pin is set to logic 0, the sdi, sdo, and sclk pins have the fol- lowing functionality: sdi serial data in (input pin), is the user-generat- ed signal used to transfer (send) data/com- mand/address/etc. bits into the device. sdo serial data out (output pin), is the data sig- nal used to read output data bits from the device?s registers. sclk serial clock (input pin), is the serial bit-clock which controls the transfer rate of data to/from the adc?s serial port. to accommodate op- to-isolators, sclk is designed with a schmitt-trig- ger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. additionally, sdo is capable of sinking or sourcing up to 5 ma to directly drive an opto-isolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourcing 5 ma. 4.3 serial read and write the state machine decodes the command word as it is received. data is written to and read from the CS5460A by using the register read/write com- mand. figure 1 illustrates the serial sequence nec- essary to write to or read from the serial port buffers. as shown in figure 1, a transfer of data is always initiated by sending the appropriate 8-bit command (msb first) to the serial port (sdi pin). it is important to note that some commands use in- formation from the cycle-count register and con- figuration register to perform the function. for those commands, it is important that the correct in- formation is written to those registers first. 4.3.1 register write when a command involves a write operation, the serial port will continue to clock in the data bits (msb first) on the sdi pin for the next 24 sclk cy- cles. command words instructing a register write must be followed by 24 bits of data. for instance, to write the configuration register, the command (0x40) is transmitted to initiate a write to the con- figuration register. the cs 5460a will acquire the serial data input from the sdi pin after 24 pulses on the sclk pin. once the data is received, the state machine writes the data to the configuration register and then waits to receive another valid command. 4.3.2 register read when a read command is initiated, the serial port will start transferring register content bits (msb first) on the sdo pin for the next 8, 16, or 24 sclk cycles. command words instructing a register read may be terminated at 8-bit boundaries (e.g., read transfers may be 8, 16, or 24 bits in length). also, data register reads allow ?command chaining?, in which the micro-controller is allowed to send a new command while reading register data. the new command will be acted upon immediately and could possibly terminate the first register read. for example, if a command word is sent to the state machine to read one of the output registers, then after pulsing sclk for 16-bits of data, a second write command word (e.g., to clear the status reg- ister) may be pulsed on to the sdi line at the same time the last 8-bits of data (from the first read com- mand) are pulsed from the sdo line. during the read cycle, the sync0 command (nop) should be strobed on the sdi port while clocking the data from the sdo port. 4.4 system initialization a software or hardware reset can be initiated at any time. the software reset is initiated by writing a logic 1 to the rs (reset system) bit in the con- figuration register, which automatically returns to logic 0 after reset. at the end of the 32 nd sclk (i.e., 8 bit command word and 24 bit data word) in- ternal synchronization delays the loading of the configuration register by 3 or 4 dclk cycles. then the reset circuit initiates the reset routine on the 1 st falling edge of mclk. a hardware reset is initiated when the reset pin is forced low for at least 50 ns. the reset signal is asynchronous, requiring no mclks for the part to detect and store a reset event. the reset pin is a schmitt trigger input, which allows it to accept
CS5460A ds487f4 43 slow rise times and/or noisy control signals. (it is not uncommon to experience temporary periods of abnormally high noise and/or slow, gradual resto- ration of power, during/after a power ?black-out? or power ?brown-out? ev ent.) once the reset pin is de-asserted, the internal reset circuitry remains ac- tive for 5 mclk cycles to insure resetting the syn- chronous circuitry in the device. the modulators are held in reset for 12 mclk cycles after reset is de-asserted . after a hardware or software reset, the internal registers (some of which may drive out- put pins) will be reset to their default values on the first mclk received after detecting a reset event (see table 3). the CS5460A will then assume its active state. (the term active state , as well as the other possible power states of the CS5460A, are described in section 4.6). the reader should refer to section 5 for a complete description of the registers listed in table 3. 4.5 serial port initialization it is possible for the serial interface to become un- synchronized with respect to the sclk input. if this occurs, any attempt to clock valid CS5460A commands into the serial interface will result in ei- ther no operation or unexpected operation be- cause the CS5460A will not interpret the input command bits correctly. the CS5460A?s serial port must then be re-initialized. to initialize the serial port, any of the following actions can be performed: 1) power on the CS5460A. (or if the device is al- ready powered on, recycle the power.) 2) hardware reset. 3) issue the serial port initialization sequence , which is performed by clocking 3 (or more) sync1 command bytes (0xff) followed by one sync0 command byte (0xfe) to the serial interface. 4.6 CS5460A power states active state denotes the operation of CS5460A when the device is fully powered on (i.e., not in sleep state or stand-by state). performing any of the following actions will insure that the CS5460A is operating in the active state: 1) power on the CS5460A. (or if the device is al- ready powered on, recycle the power.) 2) hardware reset 3) software reset in addition to the three actions listed above, if the device is operating in sleep state or stand-by state, waking up the device out of sleep state or stand-by state (by issuing the power-up/halt command) will also insure that the device is set into active state. but in order to send the power-up/halt command to the device, the serial port has to be initialized. therefore, successful wake-up of the device can be insured by writing the serial port initialization se- quence to the serial interface, prior to writing the power-up/halt command. for a description of the sleep power state and the stand-by power state, see the power down com- mand, located in section 4.1. configuration register: 0x000001 dc offset registers: 0x000000 gain registers 0x400000 pulse-rate register: 0x0fa000 cycle-counter register: 0x000fa0 timebase register: 0x800000 status register: (see section 5) mask register: 0x000000 control register: 0x000000 ac offset registers: 0x000000 power offset register: 0x000000 all data registers: 0x000000 all unsigned data registers 0x000000 table 3. default register values upon reset event
CS5460A 44 ds487f4 5. register descriptions note: 1. ** ?default? => bit st atus after software or hardware reset 2. note that all registers can be read from, and written to. 5.1 configuration register address: 0 default** = 0x000001 k[3:0] clock divider. a 4 bit binary number used to di vide the value of mclk to generate the internal clock dclk. the internal clock frequency is dclk = mclk/k. the value of k can range be- tween 1 and 16. note that a value of ?0000? will set k to 16 (not zero). icpu inverts the cpuclk clock. in order to reduce the level of noise present when analog signals are sampled, the logic driven by cpuclk should not be active during the sample edge. 0 = normal operation (default) 1 = minimize noise when cpuclk is driving rising edge logic ihpf control the use of the high pass filter on the current channel. 0 = high-pass filter is disabled. if vhpf is set, use all-pass filter. otherwise, no filter is used. (default) 1 = high-pass filter is enabled. vhpf control the use of the high pass filter on the voltage channel. 0 = high-pass filter is disabled. if ihpf is set, use all-pass filter. otherwis e, no filter is used. (default) 1 = high-pass filter enabled 23 22 21 20 19 18 17 16 pc6 pc5 pc4 pc3 pc2 pc1 pc0 gi 15 14 13 12 11 10 9 8 ewa res res si1 si0 eod dl1 dl0 76543210 rs vhpf ihpf icpu k3 k2 k1 k0 current channel voltage channel cycle-counter registe status register (1 24) serial interface mask register (1 24) unsigned output registers (2 24) (i , v ) command word state machine transmit buffer receive buffer signed output registers (4 24) (i, v, p, e) rms rms 24-bit sdi cs sdo sclk int ac offset register (1 x 24) ac offset register (1 x 24) control register (1 x 24) power offset register (1 x 24) configuration register (1 24) pulse-rat e register (1 24) offset register (1 24) dc offset register (1 24) dc gain register (1 24) ac/dc gain register (1 24) ac/dc r(124) timebase cal. register (1 x 24) figure 21. CS5460A register diagram
CS5460A ds487f4 45 rs start a chip reset cycle when set 1. the reset cy cle lasts for less than 10 xin cycles. the bit is automatically returned to 0 by the reset cycle. dl0 when eod = 1, edir becomes a user defined pin. dl0 sets the value of the edir pin. default = '0' dl1 when eod = 1, eout becomes a user defined pin. dl1 sets the value of the eout pin. default = '0' eod allows the eout and edir pins to be controlled by the dl0 and dl1 bits. eout and edir can also be accessed using the status register. 0 = normal operation of the eout and edir pins. (default) 1 = dl0 and dl1 bits control the eout and edir pins. si[1:0] soft interrupt configuration. select the de sired pin behavior for indication of an interrupt. 00 = active low level (default) 01 = active high level 10 = falling edge (int is normally high) 11 = rising edge (int is normally low) res reserved. these bits must be set to zero. ewa allows the output pins of eout and edir of multiple chips to be connected in a wire-and, us- ing an external pull-up device. 0 = normal outputs (default) 1 = only the pull-down device of the eout and edir pins are active gi sets the gain of the current pga 0 = gain is 10 (default) 1 = gain is 50 pc[6:0] phase compensation. a 2?s complement number used to set the delay in the voltage channel. when mclk = 4.096 mhz and k = 1, the phase adjust ment range is about -2.8 to +2.8 degrees and each step is about 0.04 degrees (this assume s that the power line frequency is 60 hz). if (mclk / k) is not 4.096 mhz, the values for the range and step size should be scaled by the factor 4.096 mhz / (mclk / k). default setting is 0000000 = 0.0215 degrees phase delay (when mclk = 4.096 mhz).
CS5460A 46 ds487f4 5.2 current channel dc offset register and voltage channel dc offset register address: 1 (current channel dc offset register) 3 (voltage channel dc offset register) default** = 0.000 the dc offset registers are initialized to zero on reset, allowing the device to function and perform measure- ments. the register is loaded after one computation cycle with the current or voltage offset when the proper input is applied and the dc calibration comm and is received. drdy will be assert ed at the end of the calibration. the register may be read and stored so the register may be restored with the desired system offset compensa- tion. the value is in the range full scale. the numeric format of this register is two?s complement notation. 5.3 current channel gain register and voltage channel gain register address: 2 (current channel gain register) 4 (voltage channel gain register) default** = 1.000 the gain registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. the gain registers hold the result of either the ac or dc ga in calibrations, whichever was most recently performed. if dc calibration is performed, the register is loaded a fter one computation cycle with the system gain when the proper dc input is applied and the calibration command is received. if ac calibration is performed, then after ~(6n + 30) a/d conversion cycles (where n is the value of the cycle-count register) the register(s) is loaded with the system gain when the proper ac input is applie d and the calibration command is received. drdy will be asserted at the end of the calibration. the register may be read and stored so the register may be restored with the desired system offset compensa tion. the value is in the range 0.0 gain < 4.0. 5.4 cycle count register address: 5 default** = 4000 the cycle count register value (den oted as ?n?) specifies the number of a/d conversion cycles per computation cycle . for each computation cycle, the updated results in the rms and energy registers are computed using the most recent set of n continuous instantaneous volt age/current samples. when the device is commanded to operate in ?continuous computation cycles? data ac quisition mode, the computation cycle frequency is (mclk / k) / (1024 ? n) where mclk is master clock input frequency (into xin / xout pins), k is the clock di- vider value (as specified in the configuration re gister), and n is cycl e count register value. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0
CS5460A ds487f4 47 5.5 pulse-rate register address: 6 default** = 32000.00hz the pulse-rate register determines the frequen cy of the train of pul ses output on the eout pin. each eout pulse represents a predete rmined magnitude of real (b illable) energy. the register?s smallest valid value is 2 -4 but can be in 2 -5 increments. 5.6 i,v,p,e signed output register results address: 7 - 10 these signed registers c ontain the last value of the measured results of i, v, p, and e. the results are in the range of -1.0 i, v, p, e < 1.0. the value is represented in two's complement notation, with the binary point place to the right of the msb (which is the sign bit). i, v, p, and e are output resu lts registers which contain signed values. note that the i, v, and p registers are updated every conversion cycle, while the e register is only updated after each computation cycle. the numeric format of this register is two?s complement notation. 5.7 i rms , v rms unsigned output register results address: 11,12 these unsigned registers contain the last value of the calculated results of i rms and v rms . the results are in the range of 0.0 i rms ,v rms < 1.0. the value is represented in binary notation, with the binary point place to the left of the msb. i rms and v rms are output result registers which contain unsigned values. 5.8 timebase calibration register address: 13 default** = 1.000 the timebase calibration register is in itialized to 1.0 on reset, allowing the device to function and perform com- putations. the register can be loaded with the clock frequency error to compensate for a gain error caused by the crystal/oscillator tolerance. the value is in the range 0.0 tbc < 2.0. msb lsb 2 18 2 17 2 16 2 15 2 14 2 13 2 12 2 11 ..... 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23
CS5460A 48 ds487f4 5.9 power offset register address: 14 default** = 0.000 this offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the energy register. the numeric fo rmat of this register is two?s complement notation. this register can be used to offset contributions to th e energy result that are caus ed by undesirable sources of energy that are inherent in the system. 5.10 current channel ac offset regist er and voltage channel ac offset register address: 16 (current channel ac offset register) 17 (voltage channel ac offset register) default** = 0.000 the ac offset registers are initialized to zero on reset, allowing the device to function and perform measure- ments. first, the ground-level input should be applied to the inputs. then the ac offset calibration command is should be sent to the CS5460A. after ~(6n + 30) a/d conversion cycles (where n is the value of the cy- cle-count register), the gain register(s) is loaded with th e square of the system ac offset value. drdy will be asserted at the end of the calibration. the register may be read and stored so the register may be restored with the desired system offset compensation . note that this regi ster value represents the square of the ac cur- rent/voltage offset. 5.11 status register and mask register address: 15 (status register) 26 (mask register) default** = binary: 0000000 0000000xxxx000001 (status register) {x = state depends on device revision} binary: 000000000000000000000000 (mask register) the status register indicate s the condition of the chip. in normal operat ion writing a '1' to a bit will cause the bit to go to the '0' state. writin g a '0' to a bit will maintain t he status bit in its current stat e. with this feature the user can write logic ?1? values back to th e status register to selectively clear only those bits that have been re- solved/registered by the system mcu, without concern of clearing any newly set bits. even if a status bit is masked to prevent the interr upt, the corres ponding status bit will still be set in the status register so the user can poll the status. the mask register is used to cont rol the activation of the int pin. placing a logic '1' in the mask register will msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 ..... 2 -30 2 -31 2 -32 2 -33 2 -34 2 -35 2 -36 23 22 21 20 19 18 17 16 drdy eout edir crdy math res ior vor 15 14 13 12 11 10 9 8 pwor iror vror eor eoor res id3 id2 76543210 id1 id0 wdt vod iod lsd 0 ic
CS5460A ds487f4 49 allow the corresponding bit in the status register to activate the int pin when the status bit becomes active. ic invalid command. norma lly logic 1. set to logic 0 when the part is given an invalid command. can be deactivated only by sending a port initializ ation sequence to the serial port (or by exe- cuting a software/hardware reset). when writing to the status register, this bit is ignored. lsd low supply detect. set when the voltage at th e pfmon pin falls below the low-voltage thresh- old (pmlo), with respect to va- pin. for a given part, pmlo can be as low as 2.3 v. lsd bit cannot be permanently reset until the voltage at pfmon pin rises back above the high-voltage threshold (pmhi), which is typically 100mv abov e the device?s low-volt age threshold. pmhi will never be greater than 2.7 v. iod modulator oscillation detect on the current channel. set when the modulator oscillates due to an input above full scale. note that the level at which the modu lator oscillates is significantly higher than the current channel?s differential input voltage range. vod modulator oscillation detect on the voltage channel. set when t he modulator oscillates due to an input above full scale. note that the level at which the modu lator oscillates is significantly higher than the current channel?s differential input voltage range. note: the iod and vod bits may be ?falsely? triggered by very brief voltage spikes from the power line. this event should not be confused with a dc overload situation at the inputs, when the iod and vod bits will re-assert themselves even after being cleared, multiple times. wdt watch-dog timer. set when there has been no reading of the energy register for more than 5 seconds. (mclk = 4.096 mhz, k = 1) to clear this bit, first read the energy register, then write to the status register with this bit set to logic '1'. when mclk/k is not 4.096 mhz, the time duration is 5 * [4.096 mhz / (mclk/k)] seconds. id3:0 revision/version identification. eoor the internal eout energy accumulation register went out of range. note that the eout en- ergy accumulation register is different than t he energy register available through the serial port. this register cannot be read by the user. assertion of this bit can be caused by having an output rate that is too small for the power being measured. the problem can be corrected by specifying a higher frequency in the pulse-rate register. eor energy out of range. set when the energy regi ster overflows, because the amount of energy that has been accumulated during the pending co mputation cycle is greater than the register?s highest allowable positive value or below the register?s lowest allowable negative value. vror rms voltage out of range. set when the calibrated rms voltage va lue is too large to fit in the rms voltage register. iror rms current out of range. set when the calibrate d rms current value is too large to fit in the rms current register. pwor power calculation out of range. set when the magnitude of the calculated power is too large to fit in the instantaneous power register. vor voltage out of range. ior current out of range. set when the magnitude of the calibrated current value is too large or too small to fit in the inst antaneous current register. math general computation indicates that a divide o peration overflowed. this can happen normally in the course of computation. if this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored.
CS5460A 50 ds487f4 crdy conversion ready. indicates a new conversion is ready. this will occur at the output word rate, which is usually 4 khz. edir set whenever the eout bit asserted (see below) if the accumulated energy is negative. eout indicates that enough positive/negative ener gy has been reached within the internal eout en- ergy accumulation register (not accessible to user) to mandate the generation of one or more pulses on the eout pin (if enabled, see configuration register ). the energy flow may indicate negative energy or positive energy. (the sign is determined by the edir bit, described above). this eout bit is cleared automatically when t he energy rate drops below the level that produc- es a 4 khz eout pin rate. the bit can also be cleared by writing to the status register. this status bit is set with a maxi mum frequency of 4 khz (when mclk/k is 4.096 mhz). when mclk/k is not equal to 4.096 mhz, the user s hould scale the pulse-rate by a factor of 4.096 mhz / (mclk/k) to get the actual pulse-rate. drdy data ready. when running in ?single computat ion cycle? or ?continuous computation cycles? data acquisition modes, this bi t will indicate the end of comput ation cycles. when running cali- brations, this bit indicates that the calibration sequence has completed, and the results have been stored in the offset or gain registers. 5.12 control register address: 28 default** = 0x000000 stop 1 = used to terminate the new eeboot sequence. res reserved. these bits must be set to zero. mech 1 = widens eout and edir pulses for mechanical counters. intl 1 = converts the int output to open drain configuration. sync 1 = forces internal a/d conver ter clock to synchronize to the initiation of a conversion command. nocpu 1 = converts the cpuclk output to a one- bit output port. reduces power consumption. noosc 1 = saves power by disabling the crystal oscillator for external drive. step 1 = enables stepper-motor signals on the eout /edir pins. 23 22 21 20 19 18 17 16 resresresresresresresres 15 14 13 12 11 10 9 8 res res res res res res res stop 76543210 res mech res intl sync nocpu noosc step
CS5460A ds487f4 51 6. pin descriptions 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 crystal out xout cpu clock output cpuclk positive digital supply vd+ digital ground dgnd serial clock input sclk serial data output sdo chip select cs mode select mode differential voltage input vin+ differential voltage input vin- voltage reference output vrefout voltage reference input vrefin xin crystal in sdi serial data input edir energy direction indicator eout energy output int interrupt reset reset nc no connect pfmon power fail monitor i in+ differential current input i in- differential current input va+ positive analog supply va- analog ground clock generator crystal out crystal in 1,24 xout, xin - a gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. alternatively, an external (cmos compatible clock) can be supplied into xin pin to provide the system clock for the device. cpu clock output 2 cpuclk - output of on-chip oscillator which can drive one standard cmos load. control pins and serial data i/o serial clock input 5 sclk - a clock signal on this pin determines the input and output rate of the data for the sdi and sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will re cognize clocks only when cs is low. serial data output 6 sdo - sdo is the output pin of the serial data port. its output will be in a high impedance state when cs is high. chip select 7 cs - when low, the port will recognize sclk. an active high on this pin forces the sdo pin to a high impedance state. cs should be changed when sclk is low. mode select 8 mode - when at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial eeprom to receive co mmands and settings. when at logic low, the CS5460A assumes normal ?host mode? operation. this pin is pulled down to logic low if left unconnected, by an in ternal pull-down resistor to dgnd. interrupt 20 int - when int goes low it signals that an enabled event has occurred. int is cleared (logic 1) by writing the appropriate command to the CS5460A. energy output 21 eout - the energy output pin output a fixed-width pulse rate output with a rate (pro- grammable) proportional to real (billable) energy. energy direction indicator 22 edir - the energy direction indicator indicates if the measured energy is negative. serial data input 23 sdi - the input pin of the serial data port. data will be input at a rate determined by sclk. measurement and reference input differential voltage inputs 9,10 vin+, vin- - differential analog input pins for voltage channel.
CS5460A 52 ds487f4 voltage reference output 11 vrefout - the on-chip voltage reference is output from this pin. the voltage reference has a nominal magnitude of 2.5 v and is reference to the va- pin on the converter. voltage reference input 12 vrefin - the voltage input to this pin establishes the voltage reference for the on-chip modulator. differential current inputs 15,16 iin+, iin- - differential analog input pins for current channel. power supply connections positive digital supply 3 vd+ - the positive digital supply is nominally +5 v 10% relative to dgnd. digital ground 4 dgnd - the common-mode potential of digital ground must be equal to or above the common-mode potential of va-. negative analog supply 13 va- - the negative analog supply pin must be at the lowest potential. positive analog supply 14 va+ - the positive analog supply is nominally +5 v 10% relative to va-. power fail monitor 17 pfmon - the power fail monitor pin monitors the analog supply. typical threshold level (pmlo) is 2.45 v with respect to the va- pin. if pfmon voltage threshold is tripped, the lsd (low-supply detect) bit is set in the status register. once the lsd bit has been set, it will not be able to be reset until the pfmo n voltage increases ~100 mv (typical) above the pmlo voltage. theref ore, there is hysteresis in the pfmon function. reset 19 reset - when reset is taken low, all internal registers are set to their default states. other no connection 18 nc - no connection. pin should be left floating.
CS5460A ds487f4 53 7. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.084 -- -- 2.13 a1 0.002 0.006 0.010 0.05 0.13 0.25 a2 0.064 0.068 0.074 1.62 1.73 1.88 b 0.009 -- 0.015 0.22 -- 0.38 2,3 d 0.311 0.323 0.335 7.90 8.20 8.50 1 e 0.291 0.307 0.323 7.40 7.80 8.20 e1 0.197 0.209 0.220 5.00 5.30 5.60 1 e 0.022 0.026 0.030 0.55 0.65 0.75 l 0.025 0.03 0.041 0.63 0.75 1.03 0 4 8 0 4 8 jedec #: mo-150 controlling dimension is millimeters. 24l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
CS5460A 54 ds487f4 8. ordering information CS5460A-bs 24-pin ssop -40 to 85 c CS5460A-bsz 24-pin ssop -40 to 85 c lead free 9. revision history revision date changes f2 september 2004 added lead free part numbers f3 august 2005 updated legal notice. f4 november 2007 changed pssr for voltage channel from 48 db min. to 65 db typical. contacting cirrus logic support for all product questions and inquiries contact a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risk s of death, personal injury, or severe prop- erty or environmental damage ("critical ap plications"). cirrus products are not de signed, authorized or warranted for use in products surgically implante d into the body, automo tive safety, security devices, life support products or other criti- cal. inclusion of cirrus products in such applications is under stood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any ci rrus product that is used in such a ma nner. if the custome r or customer's cus- tomer uses or permits th e use of cirrus products in criti cal applications, custome r agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a registered trademark of motorola, inc. microwire is a trademark of national semiconductor corporation.

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